Robert Yung

Evaluation of a Commercial Microprocessor

Robert Yung, R. Yung, 1998 .

UltraSPARC: the next generation superscalar 64-bit SPARC

Marc Tremblay, L. Yang, Robert B. Garner, 1995, Digest of Papers. COMPCON'95. Technologies for the Information Superhighway.

Caching processor general registers

Neil C. Wilhelm, Robert Yung, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

Design of the UltraSPARC Instruction Fetch Unit

Robert Yung, 1996 .

Extending a Prolog architecture for high performance numeric computations

Yale N. Patt, Alvin M. Despain, Robert Yung, 1989, [1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track.

An integrated prolog architecture for symbolic and numeric executions

Alvin M. Despain, Robert Yung, A. Despain, 1991, Annals of Mathematics and Artificial Intelligence.

The importance of process technology to microarchitecture

Robert Yung, 1996, CSUR.

An Extended Prolog Architecture for Integrated Symbolic and Numerical

Alvin M. Despain, Robert Yung, Yale N. Paul, 1988 .

Delayed cache writing a storage command

Guillermo Maturana, Robert Yung, 1995 .

Design decisions influencing the UltraSPARC's instruction fetch architecture

Robert Yung, 1996, MICRO.