Jae-sun Seo

发表

An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks

Yu Cao, Sarma Vrudhula, Yufei Ma, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect

David Blaauw, Himanshu Kaul, Ram Krishnamurthy, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning

Yandong Luo, Xiaoyu Sun, Shimeng Yu, 2019, IEEE Micro.

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2020, IEEE Journal of Solid-State Circuits.

Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators

Jae-sun Seo, Xiaoyang Mi, Hesam Fathi Moghadam, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2018, 2018 IEEE Symposium on VLSI Technology.

Guest Editors’ Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning

Yu Cao, Xin Li, Jae-sun Seo, 2019, ACM J. Emerg. Technol. Comput. Syst..

Improving efficiency in sparse learning with the feedforward inhibitory motif

Shimeng Yu, Yu Cao, Visar Berisha, 2017, Neurocomputing.

Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition

Yu Cao, Sung Kyu Lim, Jae-sun Seo, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2019, ACM Great Lakes Symposium on VLSI.

A 1.06 μW smart ECG processor in 65 nm CMOS for real-time biometrie authentication and personal cardiac monitoring

Yu Cao, Jae-sun Seo, Yang Liu, 2017, VLSIC 2017.

Two-step write–verify scheme and impact of the read noise in multilevel RRAM-based inference engine

Shimeng Yu, Jae-sun Seo, Won Bo Shim, 2020, Semiconductor Science and Technology.

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS

Yu Cao, Xiaofei He, Jae-sun Seo, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities

Jae-sun Seo, Mingoo Seok, Jiangyi Li, 2017, IEEE Journal of Solid-State Circuits.

In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter

David Blaauw, Dennis Sylvester, Jae-sun Seo, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators

Yu Cao, Sarma Vrudhula, Jae-sun Seo, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning

Shimeng Yu, Yu Cao, Jieping Ye, 2014, 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings.

Digital CMOS neuromorphic processor design featuring unsupervised online learning

Jae-sun Seo, Mingoo Seok, Jae-sun Seo, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS

David Blaauw, Dennis Sylvester, Ron Ho, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Dynamic and leakage power reduction of ASICs using configurable threshold logic gates

Sarma B. K. Vrudhula, Joseph Davis, Jae-sun Seo, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access

Jae-sun Seo, Min-Kyu Kim, Jae-sun Seo, 2020, IEEE Journal of Solid-State Circuits.

Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications

Chaitali Chakrabarti, Jae-sun Seo, Deepak Kadetotad, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Method and apparatus to enhance read accuracy in resistive crosspoint array

Shimeng Yu, Yu Cao, Sarma Vrudhula, 2015 .

Robust ultra-low voltage ROM design

David Blaauw, Dennis Sylvester, Jae-sun Seo, 2008, 2008 IEEE Custom Integrated Circuits Conference.

Reducing the Model Order of Deep Neural Networks Using Information Theory

Yu Cao, Visar Berisha, Ming Tu, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Self-Timed Regenerators for High-Speed and Low-Power Interconnect

David Blaauw, Dennis Sylvester, Jae-sun Seo, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Crosstalk-Aware PWM-Based On-Chip Links With Self-Calibration in 65 nm CMOS

David Blaauw, Dennis Sylvester, Jae-sun Seo, 2011, IEEE Journal of Solid-State Circuits.

Minimizing area and energy of deep learning hardware design using collective low precision and structured compression

Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo, 2017, 2017 51st Asilomar Conference on Signals, Systems, and Computers.

Towards a Wearable Cough Detector Based on Neural Networks

Yu Cao, Visar Berisha, Zheng Yang, 2018, 2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression

Sang Joon Kim, Jae-sun Seo, Shihui Yin, 2020, IEEE Transactions on Biomedical Circuits and Systems.

Guest Editors’ Introduction

Yu Cao, Xin Li, Jae-sun Seo, 2018, ACM J. Emerg. Technol. Comput. Syst..

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2018, Integr..

ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression

Jae-sun Seo, Gaurav Srivastava, Shihui Yin, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity

Visar Berisha, Jian Meng, Jae-sun Seo, 2020, INTERSPEECH.

A 1.06 μW smart ECG processor in 65 nm CMOS for real-time biometrie authentication and personal cardiac monitoring

Yu Cao, Minkyu Kim, Jae-sun Seo, 2019, 2017 Symposium on VLSI Circuits.

On the decreasing significance of large standard cells in technology mapping

David Blaauw, Dennis Sylvester, Igor L. Markov, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine

Yandong Luo, Shimeng Yu, Jae-sun Seo, 2020, IEEE Transactions on Electron Devices.

Online Knowledge Acquisition with the Selective Inherited Model

Frank Liu, Jae-sun Seo, Yu Cao, 2020, 2020 International Joint Conference on Neural Networks (IJCNN).

High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS

Shimeng Yu, Jae-sun Seo, Shihui Yin, 2019, IEEE Transactions on Electron Devices.

Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition

Yu Cao, Sung Kyu Lim, Jae-sun Seo, 2018, ACM J. Emerg. Technol. Comput. Syst..

C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2020, IEEE Journal of Solid-State Circuits.

Thermoelectric-based sustainable self-cooling for fine-grained processor hot spots

Carole-Jean Wu, Jae-sun Seo, Soochan Lee, 2016, 2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks

Xiaochen Peng, Shimeng Yu, Rui Liu, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Corrigendum: Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain

Gert Cauwenberghs, Johannes Schemmel, Shimeng Yu, 2019, Front. Neurosci..

Benchmarking TinyML Systems: Challenges and Direction pdf

David Patterson, Jae-sun Seo, Vijay Janapa Reddi, 2020, ArXiv.

Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS

Bertan Bakkaloglu, Jae-sun Seo, Visvesh S. Sathe, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Efficient and Modularized Training on FPGA for Real-time Applications

Yu Cao, Jae-sun Seo, Shihui Yin, 2020, IJCAI.

Low-power neuromorphic speech recognition engine with coarse-grain sparsity

Yiran Chen, Chaitali Chakrabarti, Chang Song, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Ranking the parameters of deep neural networks using the fisher information

Yu Cao, Visar Berisha, Ming Tu, 2016, 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

High-performance face detection with CPU-FPGA acceleration

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations

Chaitali Chakrabarti, Gregory K. Chen, Ram Krishnamurthy, 2017, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Bi-Level Rare Temporal Pattern Detection

Yu Cao, Jingrui He, Jae-sun Seo, 2016, 2016 IEEE 16th International Conference on Data Mining (ICDM).

Low Power and Trusted Machine Learning

Avesta Sasan, Tinoosh Mohsenin, Yanzhi Wang, 2018, ACM Great Lakes Symposium on VLSI.

Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks

Tushar Gupta, Jae-sun Seo, Mingoo Seok, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

Algorithm-Hardware Co-Design of Single Shot Detector for Fast Object Detection on FPGAs

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, −1) weights and (+1, 0) neurons

Xiaochen Peng, Shimeng Yu, Rui Liu, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

On the decreasing significance of large standard cells in technology mapping

David Blaauw, Dennis Sylvester, Igor L. Markov, 2008, ICCAD 2008.

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS

Yu Cao, Xiaofei He, Jae-sun Seo, 2017, ISCAS.

An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition

Visar Berisha, Jae-sun Seo, Shihui Yin, 2020, IEEE Journal of Solid-State Circuits.

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

Yong Liu, Bernard Brezzo, Daniel J. Friedman, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering

David Blaauw, Dennis Sylvester, Suyoung Bang, 2016, IEEE Journal of Solid-State Circuits.

Regulation Control Design Techniques for Integrated Switched Capacitor Voltage Regulators

Jae-sun Seo, Usama Awais, 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS).

Random sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays

Shimeng Yu, Yu Cao, Jae-sun Seo, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs

Yu Cao, Umit Y. Ogras, Jae-sun Seo, 2020, IEEE Design & Test.

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip

Shimeng Yu, Yu Cao, Jieping Ye, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview

Boris Murmann, Hoi-Jun Yoo, Jae-sun Seo, 2019, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Designing ECG-based physical unclonable function for security of wearable devices

Sang Joon Kim, Jae-sun Seo, Shihui Yin, 2017, 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning

Patrick Hansen, Matthew Mattina, Paul N. Whatmough, 2019, MLSys.

Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity

Shimeng Yu, Yu Cao, Jieping Ye, 2014, BICA.

On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices

Shimeng Yu, Yu Cao, Jieping Ye, 2015, IEEE Transactions on Nanotechnology.

Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing

Shimeng Yu, Yu Cao, Jae-sun Seo, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration

Shimeng Yu, Yu Cao, Jieping Ye, 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Yu Cao, Sarma Vrudhula, Jae-sun Seo, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems

Qi Wang, Jae-sun Seo, Mingoo Seok, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Performance Modeling for CNN Inference Accelerators on FPGA

Yu Cao, Sarma Vrudhula, Jae-sun Seo, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms

Meng-Fan Chang, Hai Li, Arindam Basu, 2018, IEEE J. Emerg. Sel. Topics Circuits Syst..

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Sarma B. K. Vrudhula, Jae-sun Seo, Niranjan Kulkarni, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2019, 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration

Tushar Gupta, Minkyu Kim, Jae-sun Seo, 2019, 2019 53rd Asilomar Conference on Signals, Systems, and Computers.

Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability

Jae-sun Seo, Mingoo Seok, Ioannis Kymissis, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks

Yu Cao, Sarma Vrudhula, Yufei Ma, 2016, FPGA.

Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks

Visar Berisha, Jae-sun Seo, Gaurav Srivastava, 2019, ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Inference engine benchmarking across technological platforms from CMOS to RRAM

Xiaochen Peng, Xiaoyu Sun, Shimeng Yu, 2019, MEMSYS.

A robust edge encoding technique for energy-efficient multi-cycle interconnect

David Blaauw, Himanshu Kaul, Ram Krishnamurthy, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

End-to-end scalable FPGA accelerator for deep residual networks

Yu Cao, Sarma B. K. Vrudhula, Minkyu Kim, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs pdf

Antonio Rios-Navarro, Alejandro Linares-Barranco, Jae-sun Seo, 2016, ArXiv.

Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs

Ricardo Tapiador-Morales, Antonio Rios-Navarro, Alejandro Linares-Barranco, 2017, IWANN.

A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks

Chaitali Chakrabarti, Shimeng Yu, Jae-sun Seo, 2018, 2018 IEEE International Workshop on Signal Processing Systems (SiPS).

Noise-based Selection of Robust Inherited Model for Accurate Continual Learning

Yu Cao, Frank Liu, Jae-sun Seo, 2020, 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW).

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2017, FPGA.

Automatic Compiler Based FPGA Accelerator for CNN Training

Eriko Nurvitadhi, Jae-sun Seo, Yu Cao, 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation

Jae-sun Seo, Shihui Yin, Deepak Kadetotad, 2020, IEEE Journal of Solid-State Circuits.

Analysis and optimization of CMOS switched-capacitor converters

Jae-sun Seo, Visvesh S. Sathe, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays

Jae-sun Seo, Shihui Yin, Bipin Rajendran, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Mitigating effects of non-ideal synaptic device characteristics for on-chip learning

Shimeng Yu, Yu Cao, Jieping Ye, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning pdf

Patrick Hansen, Matthew Mattina, Jae-sun Seo, 2019, ArXiv.

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI

Yong Liu, Seongwon Kim, Daniel J. Friedman, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain

Gert Cauwenberghs, Shimeng Yu, Yu Cao, 2018, Front. Neurosci..

A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware

David Blaauw, Chaitali Chakrabarti, Dennis Sylvester, 2016, Journal of Signal Processing Systems.

A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple

David Blaauw, Dennis Sylvester, Suyoung Bang, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect

David Blaauw, Dennis Sylvester, Jae-sun Seo, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks

Jae-sun Seo, Mingoo Seok, Deliang Fan, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA

Jae-sun Seo, Shreyas K. Venkataramanaiah, Han-Sok Suh, 2021, 2021 International Conference on Field-Programmable Technology (ICFPT).

End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression

Eriko Nurvitadhi, Vaughn Betz, Jae-sun Seo, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL).

RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy pdf

Chaitali Chakrabarti, Jae-sun Seo, Deliang Fan, 2021, ArXiv.

FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access

Patrick Hansen, Jae-sun Seo, Paul N. Whatmough, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL).

SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks

Chaitali Chakrabarti, Ümit Y. Ogras, Jae-sun Seo, 2021, ACM Trans. Embed. Comput. Syst..

Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks

Jae-sun Seo, Wangxin He, Bipin Rajendran, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

Minkyu Kim, Jae-sun Seo, Mingoo Seok, 2021, 2021 Symposium on VLSI Circuits.

Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks pdf

Chaitali Chakrabarti, Ümit Y. Ogras, Jae-sun Seo, 2021, ACM J. Emerg. Technol. Comput. Syst..

Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine

Xiaochen Peng, Shimeng Yu, Jae-sun Seo, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing

Xiaoyu Sun, Shimeng Yu, Jae-sun Seo, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction

Yandong Luo, Shimeng Yu, Jae-sun Seo, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).