Jin-Ku Kang

发表

Analysis of a Data Recovery Circuit with Digital Oversampling Technique

Jin-Ku Kang, 1998 .

Low-power non-coherent data and power recovery circuit for implantable biomedical devices

Jin-Ku Kang, Tae-Ho Kim, Benjamin P. Wilkerson, 2011, 2011 International SoC Design Conference.

An audio clock regenerator with a wide dividing ratio for HDMI

Jin-Ku Kang, Seung-Wuk Oh, Sang-Ho Kim, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Design of a third-order delta-sigma TDC with error-feedback structure

Jin-Ku Kang, Seong-Mun An, Kyung-Sub Son, 2019, IEICE Electron. Express.

A delay locked loop circuit with mixed-mode tuning

Jin-Ku Kang, Yeo-San Song, 1999, AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).

A High-Resolution Coarse-Fine Time-to-Digital Converter Reducing a Delay Mismatch in the Vernier Delay Line

Sang-Ho Kim, Hyung-Min Park, Jin-Ku Kang, 2009 .

A Multi-Spread Ratio Spread Spectrum Clock Generator for LCD Panel

Jin-Ku Kang, Il-Do Kim, Byeong-Jin Noh, 2006 .

A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort

Jin-Ku Kang, Jae-Wook Yoo, Seung-Won Lee, 2008 .

CMOS Clockless Wave Pipelined Adder Using Edge-Sensing Completion Detection

Jin-Ku Kang, Yong-Sung Ahn, 2004 .

Auto-delay offset cancellation technique for time difference repeating amplifier

Young-Jin Kim, Jin-Ku Kang, Kyung-Sub Son, 2014, 2014 International SoC Design Conference (ISOCC).

A CMOS clock and data recovery with two-XOR phase-frequency detector circuit

Jin-Ku Kang, Dong-Hee Kim, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier

Jin-Ku Kang, Min Kim, Kyung-Sub Son, 2018, 2018 International SoC Design Conference (ISOCC).

A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's

Jin-Ku Kang, Kyung-Sub Son, Taek-Joon An, 2016, IEICE Electron. Express.

Avoiding noise frequency interference with binary phase pulse driving and CDS for capacitive TSP controller

Jin-Ku Kang, Yong-Sung Ahn, Kyongsu Lee, 2014, IEICE Electron. Express.

3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling

Jin-Ku Kang, Sung-Sop Lee, Hyung-Wook Jang, 2005, Proceedings 2005 IEEE International SOC Conference.

A non-coherent BPSK receiver with dual band filtering for implantable biomedical devices

Jin-Ku Kang, Benjamin P. Wilkerson, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Precise Delay Generation using a Delay Chain Locked by Multiple Clock Period

Jun-Young Park, Jin-Ku Kang, 1999 .

A low power 120-to-520Mb/s clock and data recovery circuit for PWM signaling scheme

Jin-Ku Kang, Kyongsu Lee, Eunho Yang, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A low jitter clock and data recovery with a single edge sensing Bang-Bang PD

Jin-Ku Kang, Yong-Sung Ahn, Taek-Joon Ahn, 2014, IEICE Electron. Express.

A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement

Yong-Hwan Moon, Jin-Ku Kang, Tae-Ho Kim, 2011, IEICE Trans. Electron..

A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement

Jae-Young Jang, Jin-Ku Kang, Tae-Ho Kim, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

Design of Digital PLL using Binary Phase-Frequency Detector and Counter for Digital Phase Detection

Jin-Ku Kang, Jong-Seok Han, Kwan Yoon, 2012 .

A CMOS high-speed data recovery circuit using the matched delay sampling technique

Wentai Liu, Jin-Ku Kang, Ralph K. Cavin, 1997 .

Asynchronous Wave Pipelined Adder Using Edge-Sensing Completion Detection

Jin-Ku Kang, Yong-Sung Ahn, 2003 .

An Inductively Coupled Power and Data Link with Self-referenced ASK Demodulator and Wide-range LDO for Bio-implantable Devices

Jin-Ku Kang, Kyongsu Lee, Byeonggyu Park, 2017 .

A modified bang-bang phase detector for jitter reduction in clock and data recovery circuits

Jin-Ku Kang, Taek-Joon An, Sang-Soon Im, 2012 .

Spread Spectrum Clock Generator by VCO Current Modulation

Jin-Ku Kang, Wan-Sik Lim, 2007 .

2.5Gb/s Data Recovery Circuit with Transition/Non-transition Tracking Algorithm

Yong-Hwan Moon, Jin-Ku Kang, Jung-Bae Yoon, 2003 .

Design of Low Power 12Bit 80MHz CMOS D/A Converter using Pseudo-Segmentation Method

Jin-Ku Kang, Kwang-Sub Yoon, Sang-Min Lee, 2008 .

A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector

Jin-Ku Kang, Kyung-Sub Son, Nguyen Huu Tho, 2017, IEICE Electron. Express.

Fast Auxiliary Channel Design for Display Port

Ji-Hoon Jang, Yong-Hwan Moon, Jin-Ku Kang, 2011 .

Design of PCS with two stage pipelining 64B/66B Encoder/Decoder

Jin-Ku Kang, Tae-Ho Kim, Jin-Cheol Song, 2009 .

Design of Image Data Transmitter for Mobile Display Digital Interface

Jin-Ku Kang, Tae-Ho Kim, Ho-Kyung Lee, 2009 .

2× oversampling 2.5 Gbps clock and data recovery with phase picking method

Jin-Ku Kang, Yong-Hwan Moon, 2003 .

SSCG with Hershey-Kiss modulation profile using Dual Sigma-Delta modulators

Hyung-Min Park, Jin-Ku Kang, Hyun-Bae Jin, 2010, IEICE Electron. Express.

A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS

Yoon-Kyung Choi, Jinho Kim, Hyung-Min Park, 2010, 23rd IEEE International SOC Conference.

An 8B/10B encoder with a modified coding table

Jin-Ku Kang, Yong-Woo Kim, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

A 1.25Gb/s Clock Recovery Circuit using Half-rate 4X-Oversampling PFD

Jin-Ku Kang, Sung-Sop Lee, Hyung-Wook Jang, 2004 .

A 1.7 Gbps DLL-Based Clock Data Recovery for a Serial Display Interface in 0.35-μm CMOS

Hyung-Min Park, Jin-Ku Kang, Tae-Ho Kim, 2012 .

3.125Gb/s Reduced Word-aligning 1:10 Demultiplexer for Seiral Communication

Jin-Ku Kang, Ho-Kyoung Lee, 2007 .

A Spread Spectrum Clock Generator using modulation on VCO current source for SATA-II application

Jin-Ku Kang, Wansik Lim, 2007 .

Design of a 26ps, 8bit Gated-Ring Oscillator Time-to-Digital Converter using Vernier Delay Line

Hyung-Min Park, Jin-Ku Kang, Tae-Ho Kim, 2011 .

A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2

Jin-Ku Kang, Tae-Ho Kim, Dong-Kyun Kim, 2010, 23rd IEEE International SOC Conference.

A 0.42–3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition

Jin-Ku Kang, Kyung-Sub Son, Taek-Joon An, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS

Youngjin Kim, Jin-Ku Kang, Sangmin Lee, 2014, IEICE Electron. Express.

A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort

Sang-Ho Kim, Jin-Ku Kang, Kyung-Sub Son, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 5-Gb/s continuous-time adaptive equalizer and CDR using 0.18μm CMOS

Jin-Ku Kang, Tae-Ho Kim, Sang-Ho Kim, 2008, 2008 International SoC Design Conference.

Self-timed pipelining using latest arriving signal detection

Jin-Ku Kang, 2001 .

Design of a Spread Spectrum Clock Generator for DisplayPort

Jin-Ku Kang, Hyun-Chul Lee, Seung-Won Lee, 2009 .

Precise time-difference repetition for TDC with delay mismatch cancelling scheme

Jin-Ku Kang, Kyung-Sub Son, In-Seok Kong, 2015, IEICE Electron. Express.

A clock recovery circuit using half-rate 4/spl times/-oversampling PD

Jin-Ku Kang, Sung-Sop Lee, Hyung-Wook Jang, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's

Jin-Ku Kang, Kyung-Sub Son, Bum-Hee Choi, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Video denoising using overlapped motion compensation and advanced collaborative filtering

Byung Cheol Song, Tae Hwan Lee, Jin-Ku Kang, 2012, J. Electronic Imaging.

Low-Power Non-Coherent ASK & PSK Demodulators for Implantable High-Data-Rate Biomedical Devices

Jin-Ku Kang, Benjamin P. Wilkerson, 2012 .

On-chip jitter tolerance measurement technique for CDR circuits

Jin-Ku Kang, Kyung-Sub Son, Kyongsu Lee, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Way-lookup buffer for low-power set-associative cache

Jin-Ku Kang, Inhwan Lee, Sungjae Lee, 2011, IEICE Electron. Express.

A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOS

Jae-Young Jang, Hyung-Min Park, Jin-Ku Kang, 2012, 2012 International SoC Design Conference (ISOCC).

A Link Layer Design for DisplayPort Interface with State Machine Based Packet Processing

Byung Cheol Song, Ji-Hoon Jang, Jin-Ku Kang, 2015, J. Signal Process. Syst..

An ultra-low power BPSK demodulator with dual band filtering for implantable biomedical devices

Jin-Ku Kang, Benjamin P. Wilkerson, Jin-Cheol Seo, 2013, IEICE Electron. Express.

A 1.0 Gbps clock and data recovery circuit with two-XOR phase-frequency detector

Jin-Ku Kang, Dong-Hee Kim, 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

DisplayPort 1.1a Standard Based Multiple Video Streaming Controller Design

Ji-Hoon Jang, Jin-Ku Kang, Byung-Cheol Song, 2011 .

Spread spectrum clock generator for DisplayPort

Jin-Ku Kang, Hyun-Chul Lee, Suk-Won Lee, 2008, 2008 International SoC Design Conference.

A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2

Jin-Ku Kang, Taek-Joon An, Sang-Soon Im, 2012, 2012 IEEE International SOC Conference.

Implementation and Synthesis of Physical Coding Sublayer for 10GBASE-R Ethernet

Jin-Ku Kang, Jincheol Song, 2007 .

Automatic SfM-Based 2D-to-3D Conversion for Multi-Object Scenes

Byung Cheol Song, Hak Gu Kim, Jin-Ku Kang, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A real time image processor for reproduction of gray levels in dark areas on plasma display panel (PDP)

Jin-Ku Kang, Seung-Ho Park, Chang-Hoon Lee, 2002, IEEE Trans. Consumer Electron..

A CMOS 5.4/3.24-Gbps Dual-Rate CDR with Enhanced Quarter-Rate Linear Phase Detector

Jin-Ku Kang, Tae-Ho Kim, Dong-Kyun Kim, 2011 .

A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS

Young-Jin Kim, Jin-Ku Kang, Kyung-Sub Son, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A Low Power and Fully Differential 2.5㎓ 70㏈Ω CMOS TIA for Optical Communication

Jin-Ku Kang, Kihyuk Ha, 2007 .

An 1.25 & 2.5-Gbps Dual Mode SERDES for PON System

Jin-Ku Kang, Jung-Yong Lee, Il-Do Kim, 2005 .

A low power BPSK demodulator for wireless implantable biomedical devices

Jin-Ku Kang, Benjamin P. Wilkerson, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

High-speed 8B/10B encoder design using a simplified coding table

Jin-Ku Kang, Yong-Woo Kim, Beomseok Shin, 2008, IEICE Electron. Express.

A 720Mbps fast auxiliary channel design for DisplayPort 1.2

Jin-Ku Kang, Jong-Seok Han, Hyun-Bae Jin, 2010, 2010 International SoC Design Conference.

A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector

Jin-Ku Kang, Kyung-Sub Son, Kyongsu Lee, 2016, 2016 International SoC Design Conference (ISOCC).

A high-speed adaptive linear equalizer with ISI level detection using periodic training pattern

Jin-Ku Kang, Tae-Ho Kim, Taek-Joon An, 2012, 2012 International SoC Design Conference (ISOCC).

On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR

Jin-Ku Kang, Kyung-Sub Son, 2015, IEICE Electron. Express.

A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- $\mu\hbox{m}$ CMOS

Jin-Ku Kang, Yong-Hwan Moon, In-Seok Kong, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Design of DisplayPort AUX Channel

Jin-Ku Kang, Tae-Ho Kim, Kwang-Hee Yoon, 2010 .

Design of a CMOS Time to Digital Converter with 25ps Resolution

Jin-Ku Kang, Jin-Ho Choi, 2004 .

Performance Analysis of Oversampling Data Recovery Circuit (Special Section of Papers Selected from ITC-CSCC '98)

Jin-Ku Kang, 1999 .

A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS

Seungwon Lee, Jin-Ku Kang, Tae-Ho Kim, 2009, 2009 IEEE International SOC Conference (SOCC).

A DLL-based Clock Data Recovery with a modified input format

Jin-Ku Kang, Tae-Ho Kim, Sang-Ho Kim, 2010, IEICE Electron. Express.

A self-timed wave pipelined adder using data align method

Jin-Ku Kang, Byoung-Hoon Lim, 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

A 10Gb/s adaptive equalizer with ISI level measurement

Jin-Ku Kang, Tae-Ho Kim, Yong-Sung Ahn, 2012, IEICE Electron. Express.

A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection

Jin-Ku Kang, Kyung-Sub Son, Yong-Sung Ahn, 2014, IEICE Electron. Express.

A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

Jae-Young Jang, Jin-Ku Kang, Taek-Joon An, 2013 .

A Clock Regenerator using Two 2 nd Order Sigma-Delta Modulators for Wide Range of Dividing Ratio

Jin-Ku Kang, Seung-Wuk Oh, Sang-Ho Kim, 2012 .

A 5.4Gbps/3.24Gbps dual-rate CDR with Strengthened up/down pulse ratio

Jin-Ku Kang, Jae-Wook Yoo, Dong-Kyun Kim, 2009, 2009 International SoC Design Conference (ISOCC).