H. Toyoshima

发表

A 1.7-V adjustable I/O interface for low-voltage fast SRAMs

Toshiaki Yamanaka, Katsuro Sasaki, Koichiro Ishibashi, 1992 .

A voltage down converter with submicroampere standby current for low-power static RAMs

Katsuro Sasaki, Koichiro Ishibashi, H. Toyoshima, 1992 .

A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM (Special Issue on Circuit Technologies for Memory and Analog LSIs)

Yoji Nishio, Yoshitaka Kinoshita, Atsushi Hiraishi, 1997 .

FA 13.2: A 7ns 140mW 1Mb CMOS SRAM with Current Sense Amplifier

Fumio Kojima, Toshiaki Yamanaka, Akihiro Shimizu, 1990 .

A 16-Mb CMOS SRAM with a 2.3- mu m/sup 2/ single-bit-line memory cell

Toshiaki Yamanaka, K. Takasugi, N. Ohki, 1993 .

A 1.7V Adjustable I/O Interface for Low Voltage Fast SRAMs

Koichiro Ishibashi, H. Toyoshima, Toshiaki Yamanaka, 1991, 1991 Symposium on VLSI Circuits.