Bruno George de Moraes

An energy-efficient 8×8 2-D DCT VLSI architecture for battery-powered portable devices

José Luís Almada Güntzel, Vinicius S. Livramento, Bruno George de Moraes, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms

José Luís Almada Güntzel, Vinicius S. Livramento, Bruno George de Moraes, 2011, SBCCI '11.

Quality assessment of subsampling patterns for pel decimation targeting high definition video

José Luís Almada Güntzel, Ismael Seidel, Bruno George de Moraes, 2013, 2013 IEEE International Conference on Multimedia and Expo (ICME).

Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores

Bruno George de Moraes, Jose Luis Guntzel, S. Livramento, 2012 .

On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation

José Luís Almada Güntzel, André Beims Bräscher, Ismael Seidel, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

Analysis of Pel Decimation and Technology Choices to Reduce Energy on SAD Calculation

Ismael Seidel, Bruno George de Moraes, Jose Luis Guntzel, 2014 .

Comparison of 90 nm and 65 nm Logic Synthesis of a SAD Configurable VLSI Architecture

José Luís Almada Güntzel, André Beims Bräscher, Bruno George de Moraes, 2013 .