Shigeya Tanaka

发表

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Fumio Murabayashi, Tatsumi Yamauchi, Hirozi Yamada, 1996 .

Instruction fetch and dispatch scheme with flag‐in‐cache/in‐IBR

Shigeya Tanaka, Takashi Hotta, Hideo Sawamoto, 1998 .

A 120-MHz BiCMOS superscalar RISC processor

Hirozi Yamada, Kotaro Shimamura, Shigeya Tanaka, 1994 .

ISC Processor with Pseudo Vector Processing Feature

Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, 1995 .

A 70‐MHz, 32‐bit BiCMOS processor

Tatsumi Yamauchi, Shigeya Tanaka, Takashi Hotta, 1991 .

A superscalar RISC processor with pseudo vector processing feature

Kotaro Shimamura, Shigeya Tanaka, Hideo Sawamoto, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

A 3 V MMIC chip set for 1.9 GHz mobile communication systems

Shigeya Tanaka, I. Arai, Eiichi Hase, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

A multi-cycle operational signal processing core for an adaptive equalizer for magnetic system application

Shigeya Tanaka, S. Hanamura, H. Kojima, 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

An all-band TV tuner IC with 10 GHz/100 V mixed analog/digital Si bipolar technology

Shigeya Tanaka, Katsuyoshi Washio, Takeaki Okabe, 1990 .

Apparatus and method for parallel processing

Shigeya Tanaka, Kenichi Kurosawa, Tadaaki Bandoh, 1990 .

A BiCMOS 32-bit execution unit for 70 MHz VLSI computer

Tatsumi Yamauchi, Shigeya Tanaka, Takashi Hotta, 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

An adaptive equalizing maximum likelihood decoding LSI for magnetic recording systems

Shigeya Tanaka, Terumi Takashi, H. Kojima, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Instruction fetch and dispatch scheme with flag-in-cache/in-IBR

Shigeya Tanaka, Takashi Hotta, Hideo Sawamoto, 1998, Systems and Computers in Japan.

A data processor comprising an instruction unit that has a cache memory and a ROM.

Shigeya Tanaka, Takashi Hotta, Hideo Maejima, 1989 .

1.3- mu m CMOS/bipolar standard cell library for VLSI computers

Tatsumi Yamauchi, Shigeya Tanaka, Takashi Hotta, 1988 .

A high performance BiCMOS 32-bit microprocessor

Shigeya Tanaka, Takashi Hotta, Tadaaki Bandoh, 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

Fumio Murabayashi, Tatsumi Yamauchi, Hirozi Yamada, 1994 .

A semiconductor integrated circuit device with low power consumption and method for its operation

Shigeya Tanaka, Hideo Maejima, Masahiro Iwamura, 1990 .

Double-Station TV Meteor Observations in 1996

Shigeya Tanaka, Yukihide Shigeno, H. Shioi, 1997 .