Takashi Hotta

发表

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Fumio Murabayashi, Tatsumi Yamauchi, Hirozi Yamada, 1996 .

Instruction fetch and dispatch scheme with flag‐in‐cache/in‐IBR

Shigeya Tanaka, Takashi Hotta, Hideo Sawamoto, 1998 .

A 120-MHz BiCMOS superscalar RISC processor

Hirozi Yamada, Kotaro Shimamura, Shigeya Tanaka, 1994 .

ISC Processor with Pseudo Vector Processing Feature

Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, 1995 .

Active control of pneumatic vibration isolation table using two degrees of freedom controller

Takashi Hotta, Toshiro Noritsugu, Masahiro Takaiwa, 1993 .

A 70‐MHz, 32‐bit BiCMOS processor

Tatsumi Yamauchi, Shigeya Tanaka, Takashi Hotta, 1991 .

A triple redundant controller which adopts the time-sharing fault recovery method and its application to a power converter controller

Kotaro Shimamura, Takashi Hotta, Koji Sakamoto, 1998, Proceedings. Fourth IEEE Real-Time Technology and Applications Symposium (Cat. No.98TB100245).

Redundant controller and troubleshooting procedures for

Kotaro Shimamura, Takashi Hotta, Hirokazu Suzuki, 1998 .

Design philosophy of a high performance BiCOMS microprocessor

Takashi Hotta, Tadaaki Bandoh, Yasuhiro Nakatsuka, 1990 .

A 70-MHz 32-b microprocessor with 1.0- mu m BiCMOS macrocell library

Takashi Hotta, Tadaaki Bandoh, S. Iwamoto, 1989 .

A multiple sidelobe canceler using tapped delay line with Gram-Schmidt processing

Takashi Hotta, Takashi Kawai, Seiji Mano, 1999 .

3.3 V, novel circuit techniques for a 2.8-million-transistor BiCMOS RISC processor

Fumio Murabayashi, Tatsumi Yamauchi, Takashi Hotta, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Redundant controller and error recovery procedures for these

Kotaro Shimamura, Takashi Hotta, Hirokazu Suzuki, 1998 .

PLL-based BiCMOS on-chip clock generator for very high speed microprocessor

Takashi Hotta, Tetsuo Nakano, Kozaburo Kurita, 1990 .

BiCMOS Circuit Techniques for 3.3 V Microprocessors (Special Section on Low-Power and Low-Voltage Integrated Circuits)

Fumio Murabayashi, Tatsumi Yamauchi, Takashi Hotta, 1993 .

A BiCMOS 32-bit execution unit for 70 MHz VLSI computer

Tatsumi Yamauchi, Shigeya Tanaka, Takashi Hotta, 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

CMOS/bipolar circuits for 60-MHz digital processing

Takashi Hotta, Masahiro Ueno, Hideo Maejima, 1986 .

Instruction fetch and dispatch scheme with flag-in-cache/in-IBR

Shigeya Tanaka, Takashi Hotta, Hideo Sawamoto, 1998, Systems and Computers in Japan.

A study of design optimization of clock and logic circuits

Tatsumi Yamauchi, Takashi Hotta, Hideo Sawamoto, 1995 .

A data processor comprising an instruction unit that has a cache memory and a ROM.

Shigeya Tanaka, Takashi Hotta, Hideo Maejima, 1989 .

Development and Evaluation of Triple Redundant Controller for a Self-commutated Power Converter System

Kotaro Shimamura, Takashi Hotta, Koji Sakamoto, 1999 .

1.3- mu m CMOS/bipolar standard cell library for VLSI computers

Tatsumi Yamauchi, Shigeya Tanaka, Takashi Hotta, 1988 .

A high performance BiCMOS 32-bit microprocessor

Shigeya Tanaka, Takashi Hotta, Tadaaki Bandoh, 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Hi‐bicmos 32‐bit execution unit

Takashi Hotta, Masahiro Ueno, Hideo Maejima, 1988 .

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

Fumio Murabayashi, Tatsumi Yamauchi, Hirozi Yamada, 1994 .

Colossal Magnetoresistant Materials: The Key Role of Phase Separation

Takashi Hotta, Adriana Moreo, Elbio Dagotto, 2000, cond-mat/0012117.