Min-Jer Wang

发表

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study

Jeongho Cho, Vivek Chickermane, Brion L. Keller, 2013, 2013 IEEE International Test Conference (ITC).

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

Cheng-Wen Wu, Min-Jer Wang, Bing-Yang Lin, 2016, IEEE Design & Test.

A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC

Sang H. Dhong, Wei Hwang, Kevin Huang, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Novel Circuit Probing for Tiny Inductor

Hao Chen, Min-Jer Wang, Chia-Heng Tsai, 2020, 2020 IEEE International Test Conference in Asia (ITC-Asia).

A Local Parallel Search Approach for Memory Failure Pattern Identification

Cheng-Wen Wu, Min-Jer Wang, Bing-Yang Lin, 2016, IEEE Transactions on Computers.

A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB

Sang H. Dhong, Osamu Takahashi, Min-Jer Wang, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

A memory yield improvement scheme combining built-in self-repair and error correction codes

Hao Chen, Cheng-Wen Wu, Po-Yuan Chen, 2012, 2012 IEEE International Test Conference.

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology

Sang H. Dhong, Wei Hwang, Kevin Huang, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

High Quality Test Methodology for Highly Reliable Devices

Hao Chen, Min-Jer Wang, Mincent Lee, 2019, 2019 IEEE International Test Conference (ITC).

Novel adaptive probing for wafer level chip scale package

Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng, 2015, 2015 Joint e-Manufacturing and Design Collaboration Symposium (eMDC) & 2015 International Symposium on Semiconductor Manufacturing (ISSM).

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application

Saman Adham, Min-Jer Wang, Tze-Chiang Huang, 2014, IEEE Journal of Solid-State Circuits.

3D-IC interconnect test, diagnosis, and repair

Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS

Min-Jer Wang, C. H. Wu, Peter Kuoyuan Hsu, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application

Min-Jer Wang, Tze-Chiang Huang, Ashok Mehta, 2013, 2013 Symposium on VLSI Technology.

Smart GDBC Screening for High Quality IPD

Hao Chen, Min-Jer Wang, Hung-Chih Lin, 2018, 2018 e-Manufacturing & Design Collaboration Symposium (eMDC).

Testing-for-manufacturing (TFM) for ultra-thin IPD on InFO

Min-Jer Wang, Hung-Chih Lin, Tang-Jung Chiu, 2017, 2017 International Test Conference in Asia (ITC-Asia).

A novel DFT architecture for 3DIC test, diagnosis and repair

Hao Chen, Sen-Kuei Hsu, Saman Adham, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices

Hao Chen, Min-Jer Wang, Chia-Heng Tsai, 2020, 2020 IEEE International Test Conference (ITC).

Fan-out wafer level chip scale package testing

Hao Chen, Min-Jer Wang, Hung-Chih Lin, 2017, 2017 International Test Conference in Asia (ITC-Asia).

Heterogeneous Power Delivery for 7nm High-Performance Chiplet-Based Processors Using Integrated Passive Device and In-Package Voltage Regulator

Eric Soenen, Min-Jer Wang, Hung-Chih Lin, 2020, 2020 IEEE Symposium on VLSI Technology.

Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch

Hao Chen, Sen-Kuei Hsu, Min-Jer Wang, 2013, 2013 IEEE International Test Conference (ITC).

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices

Cheng-Wen Wu, Hao Chen, Min-Jer Wang, 2020, 2020 IEEE International Test Conference in Asia (ITC-Asia).

A novel test module for interconnect diagnosis enhancement and quality improvement in daisy chain test

Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng, 2013, 2013 e-Manufacturing & Design Collaboration Symposium (eMDC).

On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs

Cheng-Wen Wu, Min-Jer Wang, Bing-Yang Lin, 2014, IEEE Design & Test.

A 4-GHz universal high-frequency on-chip testing platform for IP validation

Sang H. Dhong, Kevin Huang, Min-Jer Wang, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package

Hao Chen, Cheng-Wen Wu, Yu-Chieh Huang, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package

Hao Chen, Cheng-Wen Wu, Min-Jer Wang, 2017, IEEE Design & Test.

Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill

Hao Chen, Min-Jer Wang, Chia-Heng Tsai, 2020, 2020 IEEE International Test Conference in Asia (ITC-Asia).

Wafer Level Chip Scale Package copper pillar probing

Hao Chen, Min-Jer Wang, Hung-Chih Lin, 2014, 2014 International Test Conference.

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS

Sang H. Dhong, Wei Hwang, Kevin Huang, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Redundancy architectures for channel-based 3D DRAM yield improvement

Cheng-Wen Wu, Min-Jer Wang, Bing-Yang Lin, 2014, 2014 International Test Conference.