D. Bolognesi

Development of an optimised 40 V pDMOS device by use of a TCAD design of experiment methodology

P. Moens, M. Vermandel, M. Tack, 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

I3T80: a 0.35 /spl mu/m based system-on-chip technology for 42 V battery automotive applications

P. Moens, F. De Pestel, L. Delobel, 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

Development of a robust 50V 0.35 /spl mu/m based Smart Power Technology using trench isolation

P. Moens, P. Coppens, H. De Vleeschouwer, 2003, ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings..

A unified hot carrier degradation model for integrated lateral and vertical nDMOS transistors

P. Moens, G. Van den bosch, D. Bolognesi, 2003, ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings..

Integrated VDMOS transistor with reduced JFET effect

F. De Pestel, D. Bolognesi, H. Hakim, 2006, 2006 European Solid-State Device Research Conference.