S. Choi

Low power operating bipolar TMO ReRAM for sub 10 nm era

S. J. Kim, J. H. Kim, R. Jammy, 2010, 2010 International Electron Devices Meeting.

Thermally robust Ta-doped Ni SALICIDE process promising for sub-50 nm CMOSFETs

S. Choi, J. Ku, N. Lee, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Highly manufacturable sub-100 nm DRAM integrated with full functionality

J.K. Cho, J.J. Lee, S. Choi, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

On-axis scheme and novel MTJ structure for sub-30nm Gb density STT-MRAM

Y. G. Shin, S. Choi, J. Jeong, 2010, 2010 International Electron Devices Meeting.

Integration of 28nm MJT for 8∼16Gb level MRAM with full investigation of thermal stability

J. H. Kim, S. O. Park, K. S. Kim, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.