Takashi Morie

发表

An 11b 300MS/s 0.24pJ/conversion-step Double-Sampling Pipelined ADC with on-chip full digital calibration for all nonidealities including memory effects

Takashi Morie, Takuji Miki, Toshiaki Ozeki, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A fully-integrated 0.13/spl mu/m CMOS mixed-signal SoC for DVD player applications

Takashi Morie, A. Matsuzawa, Toshihiko Takahashi, 2003 .

Pulse Modulation Techniques for Nonlinear Dynamical Systems and a CMOS Chaos Circuit with Arbitrary 1-D Maps

Takashi Morie, Makoto Nagata, Atsushi Iwata, 2004 .

An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing

Takashi Morie, Makoto Nagata, Atsushi Iwata, 2002 .

A 65nm CMOS Movable Parts Manager for optical disc system

Takashi Morie, Shiro Dosho, Shiro Sakiyama, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Analog CMOS circuit implementation of a pulse-coupled phase oscillator system and observation of synchronization phenomena

Kazuki Nakada, Takashi Morie, Kenji Matsuzaka, 2012 .

An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter

Takashi Morie, Shiro Dosho, Naoshi Yanagisawa, 2006, VLSIC 2006.

Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation

Takashi Morie, Hidetoshi Onodera, Keikichi Tamaru, 1995 .

A PWM analog memory programming circuit for floating-gate MOSFETs with 75-/spl mu/s programming time and 11-bit updating resolution

Takashi Morie, Makoto Nagata, Atsushi Iwata, 2001 .

The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer

Takashi Morie, Makoto Nagata, Atsushi Iwata, 1999 .

A PWM-mode CMOS Threshold-coupled-map Circuit Robust to Device Mismatches

Daisuke Atuti, Takashi Morie, Kazuyuki Aihara, 2014 .

A Pattern Matching Processor Using Analog-Digital Merged Architecture Based on Pulse Width Modulation

Takashi Morie, Makoto Nagata, Atsushi Iwata, 1999 .

Analog VLSI Circuits and Devices for Neuro-Inspired Time-Domain Computing

Takashi Morie, 2016 .

A Stochastic Associative Memory Using Single-Electron Tunneling Devices

Takashi Morie, Makoto Nagata, Atsushi Iwata, 1998 .

Physical design guides for substrate noise reduction in CMOS digital circuits

Takashi Morie, Makoto Nagata, Atsushi Iwata, 2001 .

A multinanodot floating-gate MOSFET circuit for spiking neuron models

Takashi Morie, Makoto Nagata, Tomohiro Matsuura, 2003 .

A time-domain analog weighted-sum calculation circuit using ferroelectric-gate field-effect transistors for artificial intelligence processors

Takashi Morie, Shigeki Sakai, Mitsue Takahashi, 2020 .

Novel line‐test methods using a subscriber line interface circuit

Takashi Morie, Yoshinori Oikawa, 1998 .

A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-/spl mu/m CMOS process

Takashi Morie, Shiro Dosho, Hirokuni Fujiyama, 2002 .

A CMOS circuit for STDP with a symmetric time window

Takashi Morie, Kazuyuki Aihara, Hideki Tanaka, 2007 .

Evaluation of a time-domain analog weighted-sum calculation circuit using FeFETs

Takashi Morie, Mitsue Takahashi, Shigeki Sakai, 2019 .

Line Test Methods Which Can Be Integrated in a Subscriber Line Interface Circuit

Takashi Morie, Yoshinori Oikawa, 1996 .

A -90dBc@10kHz phase noise fractional-N frequency synthesizer with accurate loop bandwidth control circuit

Takashi Morie, Shiro Dosho, Kouji Okamoto, 2005, VLSIC 2005.

Evaluation of analog memory characteristics of FeFET for Time-domain weighted-sum calculation

Takashi Morie, Shigeki Sakai, Mitsue Takahashi, 2017 .

A study on subscriber-line disconnection test method which can discriminate plural disconnection points

Takashi Morie, Yoshinori Oikawa, Takahiko Kashihara, 1996 .

An analog CMOS circuit for spiking neuron models

Takashi Morie, Kazuyuki Aihara, Hideki Tanaka, 2006 .