Tushar Gheewala

The economics of scan-path design for testability

Prab Varma, Tushar Gheewala, T. Gheewala, 1994, J. Electron. Test..

A unifying methodology for intellectual property and custom logic testing

Prab Varma, Tushar Gheewala, Sandeep Bhatia, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

ATPG based on a novel grid-addressable latch element

Tushar Gheewala, Susheel J. Chandra, Kerry Pierce, 1991, 28th ACM/IEEE Design Automation Conference.

For Test Automation, Silicon is Free

Tushar Gheewala, 1991, 1991, Proceedings. International Test Conference.

Delay testing using a matrix of accessible storage elements

Prab Varma, Tushar Gheewala, 1993, Proceedings of IEEE International Test Conference - (ITC).