Fumio Horiguchi

发表

A Circular Output Protection Device using Bipolar Action

Masaki Momodomi, Fumio Horiguchi, Mitsugi Ogura, 1987, 25th International Reliability Physics Symposium.

A spread stacked capacitor (SSC) cell for 64 Mbit DRAMs

Fumio Horiguchi, S. Inoue, Katsuhiko Hieda, 1989, International Technical Digest on Electron Devices Meeting.

A surrounding isolation-merged plate electrode (SIMPLE) cell with checkered layout for 256 Mbit DRAMs and beyond

Tohru Ozaki, Fumio Horiguchi, Katsuhiko Hieda, 1991, International Electron Devices Meeting 1991 [Technical Digest].

SESSION XVII: MEGABIT DRAMs

Fumio Horiguchi, Yasuo Itoh, 1984 .

Semiconductor memory and method for its production

Fumio Horiguchi, Katsuhiko Hieda, Takeshi Hamamoto, 1989 .

Dynamic semiconductor memory device and method for manufacturing the same

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1991 .

A33-ns64-MbDRAM

Fumio Horiguchi, Shigeyoshi Watanabe, Kazunori Ohuchi, 1991 .

Leaky coaxial cable for communication in high speed railway transportation

Fumio Horiguchi, Kunihiko Okamoto, Koichi Mikoshiba, 1975 .

High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1988, Technical Digest., International Electron Devices Meeting.

Noise-generation analysis and noise-suppression design techniques in megabit DRAMs

Fumio Horiguchi, Mitsugi Ogura, Koji Sakui, 1987 .

Semiconductor memory and process for its manufacture

Fumio Horiguchi, Akihiro Nitayama, Kazumasa Sunouchi, 1990 .

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

Fumio Horiguchi, Yukihito Oowaki, Shigeyoshi Watanabe, 1995 .

Dynamic random access memory (RAM), and methods of making the same

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1989 .

A 33ns 64Mb DRAM

Shigeyoshi Watanabe, Fumio Horiguchi, Yukihito Oowaki, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1991 .

A high-performance 1-Mbit dynamic RAM with a folded capacitor cell

Fumio Horiguchi, Mitsugi Ogura, Shigeyoshi Watanabe, 1986 .

High speed and compact CMOS circuits with multi-pillar surrounding gate transistors

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1989 .

A method of manufacturing a semiconductor memory

Fumio Horiguchi, Akihiro Nitayama, Kazumasa Sunouchi, 1990 .

Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1991 .

Mos random access memory having array of trench type one-capacitor memory cell

Fumio Horiguchi, Takeshi Hamamoto, 1993 .

Effects of a new trench-isolated transistor using sidewall gates

Fumio Horiguchi, Katsuhiko Hieda, Kazumasa Sunouchi, 1989 .

A 1Mb DRAM with a folded capacitor cell structure

Fumio Horiguchi, Mitsugi Ogura, Fujio Masuoka, 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Process integration for 64 M DRAM using an asymmetrical stacked trench capacitor (AST) cell

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1990, International Technical Digest on Electron Devices.

Sub-half-micrometer concave MOSFET with double LDD structure

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1992 .

A 33-ns 64-Mb DRAM

Fumio Horiguchi, Yukihito Oowaki, Shigeyoshi Watanabe, 1991 .