Thiago Raupp da Rosa

NoC Power Estimation at the RTL Abstraction Level

Fernando Gehm Moraes, Cezar Reinbrecht, Ney Laert Vilar Calazans, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

A Co-design Approach for Hardware Optimizations in Multicore Architectures Using MCAPI

Fabien Clermidy, Romain Lemaire, Thiago Raupp da Rosa, 2015, 2015 Ninth International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip.

Fast energy evaluation of embedded applications for many-core systems

Fernando Gehm Moraes, Ricardo Reis, Thiago Raupp da Rosa, 2014, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

MCAPI-compliant Hardware Buffer Manager mechanism to support communication in multi-core architectures

Fabien Clermidy, Romain Lemaire, Thiago Raupp da Rosa, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A high abstraction, high accuracy power estimation model for networks-on-chip

Leandro Soares Indrusiak, Fernando Gehm Moraes, Cezar Reinbrecht, 2009, SBCCI.

A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology

Emmanuel G. Collins, Gaël Pillonnet, Philippe Flatresse, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).