Theodore W. Manikas

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Integrated Circuit Channel Routing using a Pareto-Optimal Genetic Algorithm

Theodore W. Manikas, 2012, J. Circuits Syst. Comput..

Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells

Theodore W. Manikas, Dale Teeters, 2008, 38th International Symposium on Multiple Valued Logic (ismvl 2008).

Mission Planning Analysis using Decision Diagrams

Theodore W. Manikas, Mitchell A. Thornton, Frederick R. Chang, 2011 .

Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement

Theodore W. Manikas, Gerald R. Kane, 2002, IWLS.

A Digital Logic Design Laboratory for Electrical Engineering and Computer Science Undergraduates

Theodore W. Manikas, Gerald R. Kane, Jeff G. Kohlbeck, 2002 .

Built-in Self-Repair in a 3D die stack using programmable logic

Xi Shen, Theodore W. Manikas, R. Iris Bahar, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Genetic Algorithms vs. Simulated Annealing: A Comparison of Approaches for Solving the Circuit Partitioning Problem

Theodore W. Manikas, James T Cain, 1996 .

Evolving A Diverse Collection of Robot Path Planning Problems

Daniel A. Ashlock, Theodore W. Manikas, Kaveh Ashenayi, 2006, 2006 IEEE International Conference on Evolutionary Computation.

Channel height estimation in VLSI design

Theodore W. Manikas, L. Li, H. Jin, 2002 .

Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams

Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein, 2015, J. Multiple Valued Log. Soft Comput..

A genetic algorithm for mixed macro and standard cell placement

Theodore W. Manikas, M. H. Mickle, 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

A Genetic Algorithm for Autonomous Navigation Using Variable-Monotone Paths

Theodore W. Manikas, Roger L. Wainwright, Kaveh Ashenayi, 2009, Int. J. Robotics Autom..

System Probability Distribution Modeling Using MDDs

Stephen A. Szygenda, Shinobu Nagayama, Theodore W. Manikas, 2014, 2014 IEEE 44th International Symposium on Multiple-Valued Logic.

Repairing a 3-D Die-Stack Using Available Programmable Logic

Theodore W. Manikas, R. Iris Bahar, Jennifer Dworak, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Developing Laboratory Courses in a Resource-Constrained Environment

Theodore W. Manikas, Gerald R. Kane, Douglas E. Jussaume, 2005 .

Autonomous robot navigation system using a novel value encoded genetic algorithm

Theodore W. Manikas, T. Geisler, 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

Nanobattery-Crossbar System, A Promising Candidate for Future Nanoscale Data Storage

Theodore W. Manikas, Dale Teeters, Pravin C. Utekar, 2008 .

MODELING OF LARGE-SCALE DISASTER-TOLERANT SYSTEMS

Theodore W. Manikas, 2010 .

A genetic algorithm approach for mixed-macro and standard cell placement that directly incorporates cell membership information (circuit layout)

Marlin H. Mickle, Theodore W. Manikas, 1999 .

Autonomous local path planning for a mobile robot using a genetic algorithm

Heng-Ming Tai, Theodore W. Manikas, Roger L. Wainwright, 2004, Proceedings of the 2004 Congress on Evolutionary Computation (IEEE Cat. No.04TH8753).

On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2014, IEICE Trans. Inf. Syst..

Reliability block diagram extensions for non-parametric probabilistic analysis

Theodore W. Manikas, Mitchell A. Thornton, Philip C. Davis, 2016, 2016 Annual IEEE Systems Conference (SysCon).

Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams

Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein, 2012, 2012 IEEE 42nd International Symposium on Multiple-Valued Logic.

Embedded and real-time systems classes in traditional and distance education format

Phillip A. Laplante, Theodore W. Manikas, Mitchell A. Thornton, 2013, 2013 IEEE Frontiers in Education Conference (FIE).

Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2014, 2014 IEEE 44th International Symposium on Multiple-Valued Logic.

Spectral Response of Ternary Logic Netlists

Theodore W. Manikas, Mitchell A. Thornton, 2013, 2013 IEEE 43rd International Symposium on Multiple-Valued Logic.

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack

Theodore W. Manikas, Yi Sun, R. Iris Bahar, 2019, J. Electron. Test..

Standard Cell Partition Size Variance and its Effect on Physical Design

Theodore W. Manikas, Gerald R. Kane, 2001 .

On-chip thermal optimisation by whitespace reallocation using a constrained particleswarm optimisation algorithm

Theodore W. Manikas, Debarshi Chatterjee, T. Manikas, 2010, IET Circuits Devices Syst..

A VLSI Design Course in a Resource-Constrained Environment

Theodore W. Manikas, Gerald R. Kane, 2003 .

Using Existing Reconfigurable Logic in 3D Die Stacks for Test

Yi Sun, Xi Shen, Ping Gui, 2016, 2016 IEEE 25th North Atlantic Test Workshop (NATW).

Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2015, 2015 IEEE International Symposium on Multiple-Valued Logic.

Automated Markov-chain based analysis for large state spaces

Theodore W. Manikas, Kaitlin N. Smith, Mitchell A. Thornton, 2017, 2017 Annual IEEE International Systems Conference (SysCon).

Power-density aware floorplanning for reducing maximum on-chip temperature

Theodore W. Manikas, D. Chatterjee, T. Manikas, 2007 .

Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities

Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein, 2011, 2011 41st IEEE International Symposium on Multiple-Valued Logic.

Detecting a trojan die in 3D stacked integrated circuits

Ping Gui, Theodore W. Manikas, Alfred L. Crouch, 2017, 2017 IEEE North Atlantic Test Workshop (NATW).

An Electrical Engineering Summer Academy for Middle School and High School Students

Peter G. LoPresti, Theodore W. Manikas, Jeff Kohlbeck, 2010, IEEE Transactions on Education.

3D Ring Oscillator based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations

Theodore W. Manikas, Alfred L. Crouch, Jennifer Dworak, 2020 .

Nanoscale Power and Memory Unit Design for Nanoscale Sensor Systems

Theodore W. Manikas, Dale Teeters, 2007 .