Deog-Kyoon Jeong

发表

A 10-Gb/s optical receiver front-end with 5-mW transimpedance amplifier

Kyu-Sang Park, Byoung-Joo Yoo, Moon-Sang Hwang, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

A Modulo-FIR Equalizer for Wireline Communications

Deog-Kyoon Jeong, Gyu-Seob Jeong, Byungjun Kang, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme

Deog-Kyoon Jeong, Jaeha Kim, Won-Jun Choe, 2007, IEEE Journal of Solid-State Circuits.

6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS

Deog-Kyoon Jeong, Kwanseo Park, Minkyo Shim, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

43.3: Distinguished Paper: An Advanced Intra-Panel Interface (AiPi) with Clock Embedded Multi-Level Point-to-Point Differential Signaling for Large-Sized TFT-LCD Applications

Deog-Kyoon Jeong, Wonchan Kim, Hyoungsik Nam, 2006 .

A 960 Mbps/pin interface for skew-tolerant bus using low jitter PLL

Deog-Kyoon Jeong, Sung Joon Kim, Kyeongho Lee, 1996 .

Call Papers for September 2008 Special Issue on Circuits for Wireless and Wireline Communication

Deog-Kyoon Jeong, 2008 .

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push–Pull CML Driver in 65 nm CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Jiho Joo, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A multi-level multi-phase charge-recycling method for low-power AMLCD column drivers

Deog-Kyoon Jeong, Gyudong Kim, Jong-Seok Kim, 2000, IEEE Journal of Solid-State Circuits.

Introduction to the Special Section on the 2016 Asian Solid-State Circuits Conference (A-SSCC 2016)

Deog-Kyoon Jeong, Jaeha Kim, 2017, IEEE Journal of Solid-State Circuits.

A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS

Deog-Kyoon Jeong, Haram Ju, Han-Gon Ko, 2019, 2019 International Conference on Electronics, Information, and Communication (ICEIC).

A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission

Deog-Kyoon Jeong, Gyudong Kim, Gijung Ahn, 2000, IEEE Journal of Solid-State Circuits.

Reference Spur Reduction Techniques for a Phase-Locked Loop

Deog-Kyoon Jeong, Gyu-Seob Jeong, Han-Gon Ko, 2019, IEEE Access.

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

Deog-Kyoon Jeong, Gyu-Seob Jeong, Jiho Joo, 2015, IEEE Journal of Solid-State Circuits.

A single-chip 2.4 GHz direct-conversion CMOS transceiver with GFSK modem for Bluetooth application

Deog-Kyoon Jeong, Kang-Yoon Lee, Wonchan Kim, 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

A CMOS 3.5 Gbps continuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and high-frequency boosting

Deog-Kyoon Jeong, Jong-Sang Choi, Moon-Sang Hwang, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

Deog-Kyoon Jeong, Kwanseo Park, Jeongho Hwang, 2018, IEEE Journal of Solid-State Circuits.

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections

Kwangho Lee, Deog-Kyoon Jeong, Gyu-Seob Jeong, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Network Storage LSI Suitable for Home Network

Deog-Kyoon Jeong, Han-Kyu Lim, Jiho Han, 2004 .

Synthesisable glitch-less phase rotator with conditionally cascading scheme

Deog-Kyoon Jeong, Hyojun Kim, Kwangho Lee, 2020 .

A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller

Deok-Soo Kim, Deog-Kyoon Jeong, Heesoo Song, 2010, IEEE Journal of Solid-State Circuits.

Introduction to PLL/DLL

Deog-Kyoon Jeong, Woorham Bae, 2020 .

A Fully Integrated 0.13- $\mu$m CMOS 40-Gb/s Serial Link Transceiver

Deog-Kyoon Jeong, Jaeha Kim, Gyudong Kim, 2009, IEEE Journal of Solid-State Circuits.

A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process

Deog-Kyoon Jeong, Taeho Kim, Sang-Hyeok Chu, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

Development of a MEMS-based Acceleration Sensing Module for Electronic Stability Program

Deog-Kyoon Jeong, Dong-il Dan Cho, Taedong Ahn, 2007 .

Enhanced token bucket policer using reduced fair queuing for Ethernet access networks

Deog-Kyoon Jeong, Chul-Ki Lee, Jae-Hwa Kwak, 2007, IET Commun..

A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit

Deog-Kyoon Jeong, Heesoo Song, Sungchun Jang, 2011, 2011 IEEE International Solid-State Circuits Conference.

A Reduced-Swing Voltage-Mode Driver for Low-Power Multi-Gb/s Transmitters

Suhwan Kim, Deog-Kyoon Jeong, Heesoo Song, 2009 .

Single-Pin Driver: An Output Driver Boosting Technique for Off-Chip Bus

Deog-Kyoon Jeong, Wonchan Kim, Min-Kyu Kim, 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters

Deog-Kyoon Jeong, Wonchan Kim, Hwi-Cheol Kim, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

250 Mbps–5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 $\mu$m CMOS

Chulwoo Kim, Deog-Kyoon Jeong, Woo-Seok Choi, 2011, IEEE Journal of Solid-State Circuits.

Full-CMOS 2.4 GHz wideband CDMA transmitter and receiver with direct conversion mixers and DC-offset cancellation

Deog-Kyoon Jeong, Kang-Yoon Lee, Wonchan Kim, 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS

Deog-Kyoon Jeong, Han-Gon Ko, Chan-Ho Kye, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

Deog-Kyoon Jeong, Han-Gon Ko, Sung-Yong Cho, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and $G_{m}$ -Regulated Resistive-Feedback Driver

Deog-Kyoon Jeong, Gyu-Seob Jeong, Haram Ju, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM

Suhwan Kim, Deog-Kyoon Jeong, Hyunjoong Lee, 2013, IEEE Journal of Solid-State Circuits.

A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process

Deog-Kyoon Jeong, Gyu-Seob Jeong, Jiho Joo, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation

Deog-Kyoon Jeong, Hye-Yoon Joo, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

18.6 A 92.8%-Peak-Efficiency 60A 48V-to-1V 3-Level Half-Bridge DC-DC Converter with Balanced Voltage on a Flying Capacitor

Deog-Kyoon Jeong, Minho Choi, D. Jeong, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 3.3-V Low-Power Compact Driver for Multi-Standard Physical Layer

Jin-Hee Lee, Deog-Kyoon Jeong, Joon-Young Park, 2007 .

Practical considerations in the design and implementation of time synchronization systems using IEEE 1588

Deog-Kyoon Jeong, Jiho Han, 2009, IEEE Communications Magazine.

20-Gb/s 5-$\text{V}_{\mathrm{PP}}$ and 25-Gb/s 3.8-$\text{V}_{\mathrm{PP}}$ Area-Efficient Modulator Drivers in 65-nm CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Jun-Eun Park, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS

Deog-Kyoon Jeong, Haram Ju, Kwanseo Park, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Precoded two-dimensional coding method for low-power serial bus

Deog-Kyoon Jeong, Yeshik Shin, 1999 .

A 5 Gb/s 0.25 /spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Moon-Sang Hwang, Deog-Kyoon Jeong, Bong-Joon Lee, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A Novel 1.3 to 5 GHz Power Efficient and Low Phase Noise Digitally Controlled Oscillator

Deog-Kyoon Jeong, Anil Kavala, 2011 .

An injection-locked ADCDR with reference-less frequency tracking

Deog-Kyoon Jeong, Kwangho Lee, Hyojun Kim, 2018, 2018 International Conference on Electronics, Information, and Communication (ICEIC).

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

Deog-Kyoon Jeong, Gyu-Seob Jeong, Kwanseo Park, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A 2.44-pJ/b 1.62–10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE

Deog-Kyoon Jeong, Kwanseo Park, Jinhyung Lee, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface

Suhwan Kim, Deog-Kyoon Jeong, Jung-Hoon Chun, 2011, 2011 IEEE International Solid-State Circuits Conference.

An efficient charge recovery logic circuit

Deog-Kyoon Jeong, Yong Moon, D. Jeong, 1996, IEEE J. Solid State Circuits.

A 0.36 pJ/bit, 0.025 mm${}^{\text{2}}$, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

Deog-Kyoon Jeong, Gyu-Seob Jeong, Kwanseo Park, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level

Deog-Kyoon Jeong, Kwanseo Park, Hyojun Kim, 2019, 2019 Symposium on VLSI Circuits.

A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b

Deog-Kyoon Jeong, Inho Song, Wonchan Kim, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

A Mutual Capacitance Touch Readout IC With 64% Reduced-Power Adiabatic Driving Over Heavily Coupled Touch Screen

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2019, IEEE Journal of Solid-State Circuits.

A single-chip 2.4 GHz direct-conversion CMOS receiver for wireless local loop using one-third frequency local oscillator

Deog-Kyoon Jeong, Wonchan Kim, Jeong-Woo Lee, 2000 .

A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock

Suhwan Kim, Deog-Kyoon Jeong, Moon-Sang Hwang, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Haram Ju, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Adiabatically driven touch controller analog front-end for ultra-thin displays

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS

Suhwan Kim, Deog-Kyoon Jeong, Hyunjoong Lee, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter

Kwangho Lee, Deog-Kyoon Jeong, Han-Gon Ko, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Single-Inductor, Multiple-Channel Current-Balancing LED Driver for Display Backlight Applications

Hyun-Chang Kim, Deog-Kyoon Jeong, Jaeha Kim, 2013, IEEE Transactions on Industry Applications.

Gigabit Ethernet MAC Controller with Integrated TCP Segmentation Capability

Deog-Kyoon Jeong, Jiho Han, Yohwan Yoon, 2005 .

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards

Deog-Kyoon Jeong, Kwanseo Park, Woorham Bae, 2018, IEEE Transactions on Industrial Electronics.

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS

Deog-Kyoon Jeong, Kwanseo Park, Min-Seong Choo, 2019, 2019 Symposium on VLSI Circuits.

A Multidrop Bus Design Scheme With Resistor-Based Impedance Matching on Nonuniform Impedance Lines

Deog-Kyoon Jeong, Yohwan Yoon, D. Jeong, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

Extension of Two-Port Sneak Current Cancellation Scheme to 3-D Vertical RRAM Crossbar Array

Deog-Kyoon Jeong, Woorham Bae, Cheol Seong Hwang, 2017, IEEE Transactions on Electron Devices.

A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme

Deog-Kyoon Jeong, Jun-Eun Park, Jonghyun Oh, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs

Deog-Kyoon Jeong, Jaeha Kim, Sigang Ryu, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A Noise-Immunity-Enhanced Analog Front-End for $36\times64$ Touch-Screen Controllers With 20- $\text{V}_{\text{PP}}$ Noise Tolerance at 100 kHz

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2019, IEEE Journal of Solid-State Circuits.

Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits

Taewhan Kim, Deog-Kyoon Jeong, Yongho Lee, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range

Taeik Kim, Deog-Kyoon Jeong, Jihyun F. Kim, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

Deog-Kyoon Jeong, Woorham Bae, Byoung-Joo Yoo, 2012 .

A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2019, IEEE Access.

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection

Deog-Kyoon Jeong, Gyu-Seob Jeong, Sang-Hyeok Chu, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Woo-Rham Bae, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control

Deog-Kyoon Jeong, Kwanseo Park, Woo-Rham Bae, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

A Bandpass ΔΣ Interface IC for Sacrificial Bulk Micromachined Inertial Sensors

Deog-Kyoon Jeong, Jaeha Kim, Bong-Joon Lee, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

A 3-mW, 270-Mbps, Clock-Edge Modulated Serial Link for Mobile Displays

Deog-Kyoon Jeong, Jaeha Kim, Won-Jun Choe, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits

Deog-Kyoon Jeong, Jaeha Kim, Bong-Joon Lee, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

A Digital Readout IC with Digital Offset Canceller for Capacitive Sensors

Deog-Kyoon Jeong, Jun-Eun Park, Dong-Hyuk Lim, 2012 .

A Storage- and Power-Efficient Range-Matching TCAM for Packet Classification

Suhwan Kim, Deog-Kyoon Jeong, Joon-Young Park, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop

Deog-Kyoon Jeong, Jun-Eun Park, Gyungock Kim, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Jitter-Boundary-BasedDigital De-skew Algorithm

Deog-Kyoon Jeong, Jung-Bae Lee, Youngdon Choi, 2006 .

4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Hong-Seok Choi, 2018, ISLPED.

Design Optimization of On-Chip Inductive Peaking Structures for 0.13-$\mu{\hbox {m}}$ CMOS 40-Gb/s Transmitter Circuits

Deog-Kyoon Jeong, Jaeha Kim, Bong-Joon Lee, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery

Deog-Kyoon Jeong, Wonchan Kim, Youngdon Choi, 2003 .

A 5-Gb/s digitally controlled 3-tap DFE receiver for serial communications

Suhwan Kim, Deog-Kyoon Jeong, Woo-Yeol Shin, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

A multibit /spl Delta/-/spl Sigma/ D/A converter using a charge integrating sub-converter

Deog-Kyoon Jeong, Wonchan Kim, Daejong Kim, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

A 0.4-to-1 V Voltage Scalable $\Delta \Sigma $ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

Modeling and Simulation of the Microgyroscope Driving Loop using SPICE

Deog-Kyoon Jeong, Sang Chul Lee, Dong-il Dan Cho, 2006 .

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation

Deog-Kyoon Jeong, Gyu-Seob Jeong, Sang-Hyeok Chu, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Jeongho Hwang, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique

Deog-Kyoon Jeong, Wonchan Kim, Seung Wook Lee, 2001 .

A single chip /spl Delta/-/spl Sigma/ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem

Deog-Kyoon Jeong, Wonchan Kim, Sung Joon Kim, 1995 .

Efficient charge recovery logic

Deog-Kyoon Jeong, Yong Moon, D. Jeong, 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

A high-speed memory interface circuit tolerant to PVT variations and channel noise

Deog-Kyoon Jeong, Changsik Yoo, Wonchan Kim, 2001, Proceedings of the 27th European Solid-State Circuits Conference.

A fully-integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

Deog-Kyoon Jeong, Wonchan Kim, Kyeongho Lee, 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

Data recovery with tracking of the data eye pattern

Deog-Kyoon Jeong, Sang-Hyun Yangcheon-Gu Lee, D. Jeong, 2001 .

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop

Deog-Kyoon Jeong, Han-Gon Ko, Sung-Yong Cho, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

27.3: 1.2 Gbps GDDR3 Physical Layer for 3D AMOLED Panel

Moon-Sang Hwang, Deog-Kyoon Jeong, Sang-soo Kim, 2011 .

A Combined Clock and Data Recovery Circuit with Adaptive Cancellation of Data-Dependent Jitter

Suhwan Kim, Jin-Hee Lee, Deog-Kyoon Jeong, 2008 .

U-cache: a cost-effective solution to synonym problem

Sang Lyul Min, Deog-Kyoon Jeong, Chong-Sang Kim, 1995, Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture.

Virtual minimum potential queuing

Deog-Kyoon Jeong, Chul Ki Lee, Yong Chul Shim, 2007, J. High Speed Networks.

A single-inductor, multiple-channel current-balancing LED driver for display backlight applications

Hyun-Chang Kim, Deog-Kyoon Jeong, Jaeha Kim, 2013, 2013 IEEE Energy Conversion Congress and Exposition.

A 32 X 32-bit Adiabatic Register File With Supply Clock Generator

Deog-Kyoon Jeong, Yong Moon, 1997 .

Floating-point Multiply/Divide Unit for Denormal Processing in HW

Deog-Kyoon Jeong, Joong-Seok Moon, In-Ho Joong, 1996 .

A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 20 k-to-100kS/s Sub- $\mu$ W 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18- $\mu$ m CMOS

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

32.4 A 0.4-to-1.2V 0.0057mm2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement

Deog-Kyoon Jeong, Jun-Eun Park, Jonghyun Oh, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A fully integrated 0.13 /spl mu/m CMOS 10 Gb Ethernet transceiver with XAUI interface

Deog-Kyoon Jeong, Jaeha Kim, Bong-Joon Lee, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

Design and implementation of OTCA MAC protocol for high-speed point-to-point ring network

Deog-Kyoon Jeong, Yeshik Shin, Hyung-Rok Lee, 1998, Proceedings 23rd Annual Conference on Local Computer Networks. LCN'98 (Cat. No.98TB100260).

A clock synchronization system with IEEE 1588–2008 adapters over existing Gigabit Ethernet equipment

Hankyu Chi, Deog-Kyoon Jeong, Jiho Han, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Multi-gigabit-rate clock and data recovery based on blind oversampling

Deog-Kyoon Jeong, Jaeha Kim, 2003, IEEE Commun. Mag..

An ethernet switch architecture for bandwidth provision of broadband access networks

Deog-Kyoon Jeong, Jonghoon Lee, Sangho Yoon, 2008, IEEE Communications Magazine.

Clock dithering for electromagnetic compliance using spread spectrum phase modulation

Deog-Kyoon Jeong, Gyudong Kim, Yongsam Moon, 1999 .

A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18/spl mu/m

Deog-Kyoon Jeong, Keewook Jung, Ook Kim, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop

Suhwan Kim, Deog-Kyoon Jeong, Han-Gon Ko, 2019, 2019 Symposium on VLSI Circuits.

1.04 GBd low EMI digital video interface system using small swing serial link technique

Deog-Kyoon Jeong, Sung Joon Kim, Kyeongho Lee, 1998 .

27.7 A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time

Deog-Kyoon Jeong, Minho Choi, Chan-Ho Kye, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A power-efficient 600-mVpp voltage-mode driver with independently matched pull-up and pull-down impedances

Deog-Kyoon Jeong, Woo-Rham Bae, 2015, Int. J. Circuit Theory Appl..

A 0.015-mm$^{\text{2}}$ Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology

Taeik Kim, Deog-Kyoon Jeong, Gyu-Seob Jeong, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

Deog-Kyoon Jeong, Haram Ju, Kwanseo Park, 2016, IEEE Journal of Solid-State Circuits.

A 0.25-$\mu$m CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture

Suhwan Kim, Deog-Kyoon Jeong, Kang-Yoon Lee, 2007, IEEE Journal of Solid-State Circuits.

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

Deog-Kyoon Jeong, Kang-Yoon Lee, Wonchan Kim, 2003 .

Threaded prefetching: An adaptive instruction prefetch mechanism

Sang Lyul Min, Heonshik Shin, Deog-Kyoon Jeong, 1993, Microprocess. Microprogramming.

20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS

Deog-Kyoon Jeong, Jun-Eun Park, Gyungock Kim, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures

Suhwan Kim, Deog-Kyoon Jeong, Sung Bae Park, 2008, IEEE Transactions on Electron Devices.

Iterative self-timed multiplier with early completion

Deog-Kyoon Jeong, Do-Wan Kim, 2000, Proceedings of the 26th European Solid-State Circuits Conference.

A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation

Deog-Kyoon Jeong, Byungjun Kang, Haram Ju, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit

Deog-Kyoon Jeong, Jaeha Kim, Woo-Rham Bae, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology

Deog-Kyoon Jeong, Taeho Kim, 2012, 2012 International SoC Design Conference (ISOCC).

Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

Deog-Kyoon Jeong, Jaeha Kim, Bong-Joon Lee, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth

Deog-Kyoon Jeong, Woorham Bae, 2014, 2014 International Conference on Electronics, Information and Communications (ICEIC).

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS

Deog-Kyoon Jeong, Haram Ju, Kwanseo Park, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels

Deog-Kyoon Jeong, Kwanseo Park, Han-Gon Ko, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm

Deog-Kyoon Jeong, Gyu-Seob Jeong, Haram Ju, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Kwanseo Park, 2019, 2019 Symposium on VLSI Circuits.

A 1 Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750 MHz four-phase DLL

Deog-Kyoon Jeong, Yongsam Moon, 1999 .

Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator

Deog-Kyoon Jeong, Jaejin Park, Hojin Park, 2014, IEEE Journal of Solid-State Circuits.

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise

Deog-Kyoon Jeong, Woorham Bae, 2020 .

A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

Byoung-Joo Yoo, Deog-Kyoon Jeong, Won-Jun Choe, 2011 .

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

Deog-Kyoon Jeong, Gyu-Seob Jeong, Woo-Rham Bae, 2017, Sensors.

A 40-Gb/s transceiver in 0.13-μm CMOS technology

Hankyu Chi, Deog-Kyoon Jeong, Jaeha Kim, 2008, 2008 IEEE Symposium on VLSI Circuits.

Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation

Deog-Kyoon Jeong, Young-June Park, Byoung-Mo Moon, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applications

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A low-noise differential front-end and its controller for capacitive touch screen panels

Deog-Kyoon Jeong, Jun-Eun Park, Dong-Hyuk Lim, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method

Deog-Kyoon Jeong, Jong-Sang Choi, Moon-Sang Hwang, 2004 .

A Cmos Serial Link For 1 Gbaud Fully Duplexed Data Communication

Deog-Kyoon Jeong, Sung Joon Kim, Kyeongho Lee, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification

Suhwan Kim, Deog-Kyoon Jeong, Young-Deok Kim, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis

Deog-Kyoon Jeong, Borivoje Nikolić, Woorham Bae, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An 128-phase PLL using interpolation technique

Deog-Kyoon Jeong, Wonchan Kim, Hayun Chung, 2003 .

A 1.74mW/GHz 0.11–2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers

Suhwan Kim, Hankyu Chi, Deog-Kyoon Jeong, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization

Deog-Kyoon Jeong, Bong-Joon Lee, Moon-Sang Hwang, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A 2.5–5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

Deog-Kyoon Jeong, Han-Gon Ko, Sung-Yong Cho, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS

Kyungock Kim, Deog-Kyoon Jeong, Gyu-Seob Jeong, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler

Deog-Kyoon Jeong, Han-Gon Ko, Jonghyun Oh, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme

Deog-Kyoon Jeong, Gyu-Seob Jeong, Haram Ju, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces

Suhwan Kim, Deog-Kyoon Jeong, Han-Gon Ko, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller

Suhwan Kim, Deog-Kyoon Jeong, Gi-Moon Hong, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Woo-Rham Bae, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

An 800 Mbps multi-channel CMOS serial link with 3/spl times/ oversampling

Deog-Kyoon Jeong, Kyeongho Lee, Sung Joon Kim, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

Circuit and method for converting small-amplitude signal into total-amplitude signal

Deog-Kyoon Jeong, Masashi Hashimoto, 橋本征史, 1994 .

A Pseudo-Synchronous Skew-Insensitive I/O Scheme for High Band width Memories

Deog-Kyoon Jeong, Kyeongho Lee, Yunho Choi, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

A 1.35GHz all-digital fractional-N PLL with adaptive loop gain controller and fractional divider

Suhwan Kim, Deok-Soo Kim, Deog-Kyoon Jeong, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

A CMOS Serial Link for Fully Duplexed Data Communication(Special Issue on the 1994 VLSI Circuits Symposium)

Deog-Kyoon Jeong, Kyeongho Lee, Gijung Ahn, 1995 .

A low-power pulse position modulation transceiver

Deog-Kyoon Jeong, Woo-Rham Bae, Chang-Soo Yoon, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology

Hankyu Chi, Deog-Kyoon Jeong, Gyu-Seob Jeong, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 1.25-GBaud CMOS transceiver with on-chip terminator and voltage mode driver for Gigabit Ethernet 1000Base-X

Deog-Kyoon Jeong, Gijung Ahn, 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology

Deog-Kyoon Jeong, Woo-Rham Bae, Byoung-Joo Yoo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

A 285-fs rms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

Deog-Kyoon Jeong, Gyu-Seob Jeong, Woorham Bae, 2016 .

with DLL-Based Data-Recovery Circuit

Deog-Kyoon Jeong, Heesoo Song, Sungchun Jang, 2011 .

A $4.7\mu \mathrm{A}$ Quiescent Current Synthesizable Digital Low Dropout Regulator in 28-nm CMOS

Deog-Kyoon Jeong, Jun-Eun Park, Jonghyun Oh, 2019, 2019 International Conference on Electronics, Information, and Communication (ICEIC).

An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068pJ/b/dB 1.62-to-10Gb/s Low-Power Receiver in 40nm CMOS

Deog-Kyoon Jeong, Haram Ju, Kwanseo Park, 2020 .

A 1.3–330-MHz direct clock synthesizer for display interface using fractional multimodulus frequency divider

Deog-Kyoon Jeong, Heesoo Song, Ho Young Song, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

A 16-Gb/s injection-locked CDR in embedded clock receiver

Deog-Kyoon Jeong, Byung-Jun Kang, Chan-Ho Kye, 2018, 2018 International Conference on Electronics, Information, and Communication (ICEIC).

Design of PLL-based clock generation circuits

Randy H. Katz, Deog-Kyoon Jeong, D. A. Hodges, 1987 .

A 20-Gb/s full-rate 27-1 PRBS generator integrated with 20-GHz PLL in 0.13-μm CMOS

Deog-Kyoon Jeong, Jaeha Kim, Jeong-Kyoum Kim, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

TCAM for Packet Classification

Suhwan Kim, Deog-Kyoon Jeong, Joon-Young Park, 2006 .

56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits

Deog-Kyoon Jeong, Gyu-Seob Jeong, Sungwoo Kim, 2019, 2019 Optical Fiber Communications Conference and Exhibition (OFC).

250Mbps-5Gbps wide-range CDR with digital vernier phase shifting and dual mode control in 0.13μm CMOS

Chulwoo Kim, Byoung-Joo Yoo, Deog-Kyoon Jeong, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface

Deog-Kyoon Jeong, Woo-Rham Bae, Byoung-Joo Yoo, 2012, 2012 International SoC Design Conference (ISOCC).

An Always-On 0.53-to-13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays With Current-Mode Filter and Incremental Hybrid ΔΣ ADC

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC).

A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS

Deog-Kyoon Jeong, Woo-Rham Bae, Yoonsoo Kim, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels

Deog-Kyoon Jeong, Jun-Eun Park, Dong-Hyuk Lim, 2014, IEEE Journal of Solid-State Circuits.

An AC-powered, flicker-free, multi-channel LED driver with current-balancing SIMO buck topology for large area lighting applications

Hyun-Chang Kim, Deog-Kyoon Jeong, Jaeha Kim, 2014, 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014.

22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface

Deog-Kyoon Jeong, Han-Gon Ko, Dongkyun Kim, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A theoretical analysis of phase shift in pulse injection-locked oscillators

Deog-Kyoon Jeong, Han-Gon Ko, Sung-Yong Cho, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

A 32/spl times/32 self-timed multiplier with early completion

Deog-Kyoon Jeong, Do-Wan Kim, 1999, AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).

A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines

Suhwan Kim, Deog-Kyoon Jeong, Heesoo Song, 2009, 2009 IEEE International SOC Conference (SOCC).

A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit

Deog-Kyoon Jeong, Jun-Eun Park, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

Deog-Kyoon Jeong, Kwanseo Park, Hyojun Kim, 2020, IEEE Journal of Solid-State Circuits.

V-P cache: a storage efficient virtual cache organization

Sang Lyul Min, Heonshik Shin, Deog-Kyoon Jeong, 1993, Microprocess. Microsystems.

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

Deog-Kyoon Jeong, Kwanseo Park, Min-Seong Choo, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits

Deog-Kyoon Jeong, Yongho Lee, Taewhan Kim, 2008, ICCAD 2008.

A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control

Suhwan Kim, Deok-Soo Kim, Deog-Kyoon Jeong, 2011, IEEE Journal of Solid-State Circuits.

A 32/spl times/32-b adiabatic register file with supply clock generator

Deog-Kyoon Jeong, Yong Moon, 1998 .

A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Haram Ju, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 26.5–37.5 GHz frequency divider and a 73-GHz-BW CML buffer in 0.13μm CMOS

Suhwan Kim, Deog-Kyoon Jeong, Jaeha Kim, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique

Deog-Kyoon Jeong, Wonchan Kim, Hwi-Cheol Kim, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Design of a Transceiver Transmitting Power, Clock, and Data over a Single Optical Fiber for Future Automotive Network System

Deog-Kyoon Jeong, Haram Ju, Woorham Bae, 2017 .

29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and −65dBc reference spur using time-division dual calibration

Hankyu Chi, Deog-Kyoon Jeong, Han-Gon Ko, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

Suhwan Kim, Deok-Soo Kim, Deog-Kyoon Jeong, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Hotpads - macro-dells for gigabit I/O

Deog-Kyoon Jeong, Amnon Fisher, J. Duane Northcutt, 1994, Symposium Record Hot Interconnects II.

A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems

Deog-Kyoon Jeong, Jiho Han, 2010, IEEE Transactions on Instrumentation and Measurement.

An AC–DC LED Driver With a Two-Parallel Inverted Buck Topology for Reducing the Light Flicker in Lighting Applications to Low-Risk Levels

Hyun-Chang Kim, Deog-Kyoon Jeong, Sungwoo Kim, 2017, IEEE Transactions on Power Electronics.

11.6 A 100-TRX-channel configurable 85-to-385Hz-frame-rate analog front-end for touch controller with highly enhanced noise immunity of 20Vpp

Deog-Kyoon Jeong, Young-Ha Hwang, Jun-Eun Park, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS

Hankyu Chi, Deog-Kyoon Jeong, Dong-Wook Kim, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter

Suhwan Kim, Deog-Kyoon Jeong, Heesoo Song, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

A^3: Accelerating Attention Mechanisms in Neural Networks with Approximation

Deog-Kyoon Jeong, Jae W. Lee, Young H. Oh, 2020, 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).

A single-chip storage LSI for home networks

Deog-Kyoon Jeong, KyungTae Kim, Hankyu Lim, 2005, IEEE Commun. Mag..

An 1.4Gbps/ch LVDS Receiver with Jitter-Boundary-Based Digital De-skew Algorithm

Deog-Kyoon Jeong, Wonchan Kim, Chang-Hyun Kim, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

An 8-bit 125 MS/s CMOS folding ADC for Gigabit Ethernet LSI

Deog-Kyoon Jeong, Wonchan Kim, Jeongho Lee, 2000 .

Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits

Taewhan Kim, Deog-Kyoon Jeong, Yongho Lee, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Kwanseo Park, 2021, IEEE Access.

A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS

Deog-Kyoon Jeong, Moon-Chul Choi, Seungha Roh, 2021, 2021 18th International SoC Design Conference (ISOCC).

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration

Hankyu Chi, Deog-Kyoon Jeong, Kwanseo Park, 2021, IEEE Journal of Solid-State Circuits.

A Fast Droop-Recovery Event-Driven Digital LDO With Adaptive Linear/Binary Two-Step Search for Voltage Regulation in Advanced Memory

Deog-Kyoon Jeong, Jun-Eun Park, Sung-Yong Cho, 2022, IEEE Transactions on Power Electronics.

Auto-tracking Method with Optimal Reference Voltage for PAM-4 Receiver

Deog-Kyoon Jeong, Daeho Yun, 2021, 2021 18th International SoC Design Conference (ISOCC).

A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS

Deog-Kyoon Jeong, Haram Ju, Woosong Jung, 2021, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Stochastic Variable Gain Amplifier Adaptation for PAM-4 signaling

Deog-Kyoon Jeong, Minkyo Shim, Woonghee Lee, 2021, 2021 18th International SoC Design Conference (ISOCC).

A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Deog-Kyoon Jeong, Woorham Bae, Sung-Yong Cho, 2021 .

0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link

Deog-Kyoon Jeong, Minkyo Shim, Han-Gon Ko, 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13/spl mu/m CMOS

Deog-Kyoon Jeong, Bong-Joon Lee, Wonchan Kim, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

Silicon photonic receiver and transmitter operating up to 36 Gb/s for λ~1550 nm.

Hankyu Chi, Deog-Kyoon Jeong, Gyu-Seob Jeong, 2015, Optics express.

Reduction of pump current mismatch in charge-pump PLL

Deog-Kyoon Jeong, Moon-Sang Hwang, Jaeha Kim, 2009 .

A 6.3 mW high-SNR frame-rate scalable touch screen panel readout IC with column-parallel Σ-Δ ADC structure for mobile devices

Deog-Kyoon Jeong, Dong-Hyuk Lim, Jun-Eun Park, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 1 . 74 mW / GHz 0 . 11-2 . 5 GHz Fast-Locking , Jitter-Reducing , 180 ° Phase-Shift Digital DLL with a Window Phase Detector for LPDDR 4 Memory Controllers

Hankyu Chi, Deog-Kyoon Jeong, Woo-Yeol Shin, 2015 .

A fully-integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

Deog-Kyoon Jeong, Wonchan Kim, Kyeongho Lee, 2001, VLSIC 2001.

4-Slot, 8-Drop Impedance-Matched Bidirectional Multidrop DQ Bus With a 4.8-Gb/s Memory Controller Transceiver

Deog-Kyoon Jeong, Jung-Hoon Chun, Woo-Yeol Shin, 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- ${\rm G}_{\rm m}$ Bias

Deog-Kyoon Jeong, Gyu-Seob Jeong, Haram Ju, 2016, IEEE Journal of Solid-State Circuits.

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

Deog-Kyoon Jeong, Jeong-Kyoum Kim, Jaeha Kim, 2006, IEEE Journal of Solid-State Circuits.

A 0.6-2.5 GBaud CMOS tracked 3/spl times/ oversampling transceiver with dead-zone phase detection for robust clock/data recovery

Deog-Kyoon Jeong, Gijung Ahn, Yongsam Moon, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

Deog-Kyoon Jeong, Kyeongho Lee, Yongsam Moon, 2000, IEEE Journal of Solid-State Circuits.

A 5.6 GHz LC digitally controlled oscillator with high frequency resolution using novel quadruple resolution varactor

Deog-Kyoon Jeong, Sungchun Jang, Anil Kavala, 2010, 2010 International SoC Design Conference.

A crossbar resistance switching memory readout scheme with sneak current cancellation based on a two-port current-mode sensing.

Deog-Kyoon Jeong, Cheol Seong Hwang, Kyung Jean Yoon, 2016, Nanotechnology.

A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL

Deog-Kyoon Jeong, Gi-Moon Hong, Suhwan Kim, 2014 .

Class-AB large-swing CMOS buffer amplifier with controlled bias current

Deog-Kyoon Jeong, Joongsik Kih, Byungsoo Chang, 1993 .

Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

Deog-Kyoon Jeong, Minho Choi, 2020 .