Hussain Al-Asaad

发表

Detection and Isolation of Faulty Processors in Multiprocessor Systems via TMR-Based Time Redundant Task Scheduling

Hussain Al-Asaad, 2009, CDES.

Approaches for Monitoring Vectors on Microprocessor Buses

Hussain Al-Asaad, Hector Arteaga, 2004, ESA/VLSI.

Low power logic design via glitch estimation and power optimization

Hussain Al-Asaad, Sammy Aldeen, 2007 .

Low Power Methodologies and Challenges for PWM DC-DC Converters

Hussain Al-Asaad, Calvin Chiem, 2009, CDES.

Scalable Test Generators for High-Speed Datapath Circuits

John P. Hayes, Hussain Al-Asaad, Brian T. Murray, 1998, J. Electron. Test..

A two-phase reconfiguration strategy for extracting linear arrays out of two-dimensional architectures

Elias S. Manolakos, Hussain Al-Asaad, 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Efficient techniques for reducing error latency in on-line periodic BIST

Hussain Al-Asaad, 2009, 2009 IEEE AUTOTESTCON.

On Increasing the Observability of Modern Microprocessors

Hussain Al-Asaad, Hector Arteaga, 2005, CDES.

Real time scheduling of multiple executions of tasks to achieve fault tolerance in multiprocessor systems

Hussain Al-Asaad, H. Al-Asaad, 2014, 2014 IEEE AUTOTEST.

Design verification via simulation and automatic test pattern generation

John P. Hayes, Hussain Al-Asaad, 1995, ICCAD.

MVP: a mutation-based validation paradigm

Hussain Al-Asaad, Jorge Campos, 2005, Tenth IEEE International High-Level Design Validation and Test Workshop, 2005..

Time-Redundant Logic-Level Protection Mechanisms from Soft Errors in Digital Systems

Hussain Al-Asaad, 2010, CDES.

Improving the design and reliability of future computer systems via using intermediate values of outputs

Hussain Al-Asaad, Luis Bustamante, 2015, 2015 IEEE AUTOTESTCON.

On The Design of Fault Tolerant VLSI and WSI Non-Homogenous Multipipelines

Hussain Al-Asaad, 1998 .

ESIM: a multimodel design error and fault simulator for logic circuits

John P. Hayes, Hussain Al-Asaad, 2000, Proceedings 18th IEEE VLSI Test Symposium.

EGFC: An exact global fault collapsing tool for combinational circuits

Hussain Al-Asaad, 2005, Circuits, Signals, and Systems.

Concurrent error correction in iterative circuits by recomputing with partitioning and voting

Hussain Al-Asaad, Edward C. Czeck, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

Efficient Global Fault Collapsing for Combinational Library Modules

Hussain Al-Asaad, 2007, CDES.

Detection of soft errors through checksums in redundant execution systems

Hussain Al-Asaad, Luis Bustamante, 2015, 2015 IEEE AUTOTESTCON.

Logic Design Validation via Simulation and Automatic Test Pattern Generation

John P. Hayes, Hussain Al-Asaad, J. Hayes, 2000, J. Electron. Test..

Online BIST for Embedded Systems

John P. Hayes, Hussain Al-Asaad, Brian T. Murray, 1998, IEEE Des. Test Comput..

Survey and Evaluation of Low-Power Flip-Flops

Hussain Al-Asaad, Ahmed Sayed, 2006, CDES.

Survey and Evaluation of Low-Power Full-Adder Cells

Hussain Al-Asaad, Ahmed Sayed, 2004, ESA/VLSI.

A Novel Functional Testing and Verification Technique for Logic Circuits

Hussain Al-Asaad, Lourdes Ramirez, Ganesh Valliappan, 2005, CDES.

High-level design verification of microprocessors via error modeling

John P. Hayes, Trevor N. Mudge, Richard B. Brown, 1998, TODE.

A Comparison of NMOS to PMOS Starved Buffer Implementations for the Delay Line in a PWM DC-DC Converters

Hussain Al-Asaad, Calvin Chiem, 2010, CDES.

A New Low Power High Performance Flip-Flop

Hussain Al-Asaad, Ahmed Sayed, H. Al-Asaad, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

Mutation-based validation of high-level microprocessor implementations

Hussain Al-Asaad, Jorge Campos, 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions

Hussain Al-Asaad, Jorge Campos, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling

Hussain Al-Asaad, Alireza Sarvi, 2003, VLSI.

A simplified overview of handling faults in systems around us

Hussain Al-Asaad, 2016, 2016 IEEE AUTOTESTCON.

Survey of Memory, Timing, and Power Management Verification Methods for Multi-core Processors

Hussain Al-Asaad, Savita Patil, Sabrina Scholten, 2019, 2019 IEEE 10th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON).

Brief Review of Low-Power GPU Techniques

Hussain Al-Asaad, Pragati Sharma, 2021, Advances in Security, Networks, and Internet of Things.