Hiroyuki Morinaka

A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)

Hiroaki Suzuki, Tadashi Sumi, Hiroshi Makino, 1996 .

Leading-zero anticipatory logic for high-speed floating point addition

Koichiro Mashiko, T. Sumi, H. Suzuki, 1995 .

A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs)

Hiroaki Suzuki, Tadashi Sumi, Hiroshi Makino, 1996 .

A 64 bit carry look-ahead CMOS adder using Modified Carry Select

H. Suzuki, Hiroshi Makino, Koichiro Mashiko, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

Floating-body effects on propagation delay in SOI/CMOS LSIs

Tadashi Sumi, Koichiro Mashiko, Hiroyuki Morinaka, 1996, 1996 IEEE International SOI Conference Proceedings.

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]

Tadashi Sumi, Hiroshi Makino, Yasunobu Nakase, 1997 .

An advanced 0.5 /spl mu/m CMOS/SOI technology for practical ultrahigh-speed and low-power circuits

Tsutomu Hirao, Koichiro Mashiko, Takashi Iwamatsu, 1995, 1995 IEEE International SOI Conference Proceedings.

Leading-zero anticipatory logic for high-speed floating point addition

Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

A 286 MHz 64-b floating point multiplier with enhanced CG operation

Koichiro Mashiko, Hiroshi Makino, Y. Nakase, 1996 .