George D. Gristede

Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies

Charles A. Zukowski, Phillip Chin, George D. Gristede, 2005, Integr..

Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability

George D. Gristede, W. Hwang, P. N. Sanda, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

SynTunSys: A Synthesis Parameter Autotuning System for Optimizing High-Performance Processors

Luca P. Carloni, Matthew M. Ziegler, Hung-Yi Liu, 2019 .

Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

George D. Gristede, W. Hwang, D. F. Heidel, 1999, IEEE J. Solid State Circuits.