K. Arai

The Measure for Improving the Durability of Shin-katsushika Bridge, Tokyo Gaikan Expressway, at the Stage of Construction

Y. Koshiyama, K. Arai, Y. Abe, 2011 .

Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

H. Kitada, T. Ohba, K. Arai, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Development of sub 10-µm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory

H. Kitada, T. Ohba, T. Eshita, 2010, 2010 Symposium on VLSI Technology.

Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

H. Kitada, T. Ohba, K. Arai, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications

T. Ohba, K. Arai, T. Nakamura, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Stress sensitivity analysis on TSV structure of wafer-on-a-wafer (WOW) by the finite element method (FEM)

T. Suzuki, H. Kitada, T. Ohba, 2009, 2009 IEEE International Interconnect Technology Conference.