Katsunori Tani

Two-dimensional layout synthesis for large-scale CMOS circuits

Takashi Fujii, Tsuneo Matsuda, Katsunori Tani, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

A robust min-cut improvement algorithm based on dynamic look-ahead weighting

Katsunori Tani, 1995, ASP-DAC '95.

On area-efficient drawings of rectangular duals for VLSI floor-plan

Shoji Shinoda, Shuji Tsukiyama, Isao Shirakawa, 1991, Math. Program..

An algorithm generating all rectangular duals for VLSI floor-plan

Shuji Tsukiyama, Isao Shirakawa, Katsunori Tani, 1987, 1987 Symposium on VLSI Circuits.

A Floor Plan System Using a Rectangular Dual

Isao Shirakawa, Shuji Tsukiyama, Katsunori Tani, 1988 .

AN ALGORITHM FOR CMOS CELL / MACRO LAYOUT SYNTHESIS

Takashi Fujii, Tsuneo Matsuda, Katsunori Tani, 1992 .