M. S. Hrishikesh

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

Norman P. Jouppi, Doug Burger, Stephen W. Keckler, 2002, ISCA.

Static energy reduction techniques for microprocessor caches

Vikas Agarwal, Doug Burger, Stephen W. Keckler, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Memory Hierarchy Extensions to the SimpleScalar Tool Set

M. S. Hrishikesh, Doug Burger, Alain Kagi, 2000 .

Clock rate versus IPC: the end of the road for conventional microarchitectures

Vikas Agarwal, Doug Burger, Stephen W. Keckler, 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

Static energy reduction techniques for microprocessor caches

Vikas Agarwal, Doug Burger, Stephen W. Keckler, 2003, IEEE Trans. Very Large Scale Integr. Syst..

A new transform for the stabilization and stability testing of multidimensional recursive digital filters

M. S. Hrishikesh, P. S. Reddy, H. Damera-Venkata, 2000 .

Stabilization of 2-D recursive digital filters by the DHT method

Niranjan Damera-Venkata, M. S. Hrishikesh, P. S. Reddy, 1999 .