J. M. Solana

发表

Fully pipelined TSPC barrel shifter for high-speed applications

J. A. Michell, R. Pereira, J. M. Solana, 1995 .

Pipelined TSPC barrel shifter with scan test facilities for VLSI implementation of high speed DSP applications

J. A. Michell, J. M. Solana, R. Pereira, 1992, Proceedings Euro ASIC '92.

Programmable processor for on-line computing of inverse Haar transform

O. Martin, J. M. Solana, 2001 .

PASE-scan design: a new full-scan structure to reduce test application time

J. M. Solana, M. A. Manzano, 1999 .

Efficient test cost reduction procedure for parallel-serial scan circuits

J. M. Solana, 2001 .

Limited maximum fault-multiplicity diagnosis procedure for scan designs

J. M. Solana, M. A. Manzano, 2000 .

A New Method for Studying the Aliasing Probability in Signature Analysis Registers

J. M. Solana, N. P. Cagigal, F.J. Velasco, 2000 .

Elimination algorithm: a method for fault diagnosis in combinational circuits based on an effect-cause analysis

S. Bracho, J. A. Michell, J. M. Solana, 1986 .