Jacob Savir

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Random Pattern Testability of Memory Control Logic

Jacob Savir, 1998, IEEE Trans. Computers.

Random Pattern Testability

Gary S. Ditlow, Jacob Savir, Paul H. Bardell, 1984, IEEE Transactions on Computers.

A Multiple Seed Linear Feedback Shift Register

Jacob Savir, William H. McAnney, 1992, IEEE Trans. Computers.

VLSI Self-Testing Based on Syndrome Techniques

George Markowsky, Jacob Savir, Merlin G. Smith, 1981, ITC.

Statistical Resistance to Detection

Jacob Savir, A. Boneh, 1992, IEEE Trans. Computers.

Coefficient-based test of parametric faults in analog circuits

Zhen Guo, Jacob Savir, 2006, IEEE Transactions on Instrumentation and Measurement.

Layout Influences Testability

Jacob Savir, Thomas H. Spencer, 1985, IEEE Transactions on Computers.

Distributed BIST Architecture to Combat Delay Faults

Jacob Savir, 2000, J. Electron. Test..

Test limitations of parametric faults in analog circuits

Zhen Guo, Jacob Savir, 2003, IEEE Trans. Instrum. Meas..

MUST: multiple-stem analysis for identifying sequentially untestable faults

Qiang Peng, Jacob Savir, Miron Abramovici, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

RAM BIST

Jacob Savir, 2000, Proceedings of the 17th IEEE Instrumentation and Measurement Technology Conference [Cat. No. 00CH37066].

BIST-Based Fault Diagnosis in the Presence of Embedded Memories

Jacob Savir, 2001, VLSI Design.

The Bidirectional Double Latch (BDDL)

Jacob Savir, 1986, IEEE Transactions on Computers.

Built-In Self-Test: Milestones and Challenges

Jacob Savir, Paul H. Bardell, P. Bardell, 1993, VLSI Design.

Built-in online and offline test of airborne digital systems

Jacob Savir, 2005, IEEE Transactions on Instrumentation and Measurement.

Developments in delay testing

Jacob Savir, J. Savir, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Design for testability to combat delay faults

Jacob Savir, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Detection of intermittent faults in sequential circuits

Jacob Savir, J. Savir, 1978 .

On test and characterization of analog linear time-invariant circuits using neural networks

Zhen Guo, Yun Q. Shi, Jacob Savir, 2001, Proceedings 10th Asian Test Symposium.

ECE 251 - Digital Design

Jacob Savir, 2018 .

Broad-side delay test

Srinivas Patil, Jacob Savir, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Module Level Weighted Random Patterns

Jacob Savir, 1997, J. Electron. Test..

Identification of failing tests with cycling registers

Jacob Savir, William H. McAnney, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

Observer-based test of analog linear time-invariant circuits

Zhen Guo, Jacob Savir, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

Module Level Weighted Random Patterns

Jacob Savir, J. Savir, 1995, Proceedings of the Fourth Asian Test Symposium.

Distributed generation of weighted random patterns

Jacob Savir, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory

Jacob Savir, William H. McAnney, Salvatore R. Vecchio, 1985, ITC.

Why partial design verification works better than it should

Jacob Savir, J. Savir, 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

On broad-side delay test

Srinivas Patil, Jacob Savir, S. Patil, 1994, Proceedings of IEEE VLSI Test Symposium.

AC strength of a pattern generator

Jacob Savir, Robert F. Berry, 1992, J. Electron. Test..

Skewed-Load Transition Test: Part II, Coverage

Srinivas Patil, Jacob Savir, S. Patil, 1992, Proceedings International Test Conference 1992.

Memory chip BIST architecture

Jacob Savir, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Built In Test for VLSI: Pseudorandom Techniques

Jacob Savir, Paul H. Bardell, William H. McAnney, 1987 .

Skewed-Load Transition Test: Part I, Calculus

Jacob Savir, 1992, Proceedings International Test Conference 1992.

Distributed Generation of Weighted Random Patterns

Jacob Savir, 1999, IEEE Trans. Computers.

Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory

Jacob Savir, William H. McAnney, Salvatore R. Vecchio, 1985, ITC.

On the detectability of parametric faults in analog circuits

Zhen Guo, Jacob Savir, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

On broad-side delay test

Srinivas Patil, Jacob Savir, 1994, IEEE Trans. Very Large Scale Integr. Syst..

Algorithm-based fault detection of analog linear time-invariant circuits

Jacob Savir, Zhen Guo, 2001, IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188).

Random pattern testability of memory address logic

Jacob Savir, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On-line and off-line test of airborne digital systems: a reliability study

Jacob Savir, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Salvaging test windows in BIST diagnostics

Jacob Savir, J. Savir, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

Partitioning of digital systems

Jacob Savir, Willem M. vanCleemput, L. K. Scheffer, 1979 .

Single-clock, single-latch, scan design

Jacob Savir, Amit M. Sheth, 2003, IEEE Trans. Instrum. Meas..

Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST

Hideo Fujiwara, Yoshiyuki Nakamura, Jacob Savir, 2005, IEICE Trans. Inf. Syst..

Testing for Coupled Cells in Random-Access Memories

Jacob Savir, William H. McAnney, Salvatore R. Vecchio, 1991, IEEE Trans. Computers.

Good Controllability and Observability Do Not Guarantee Good Testability

Jacob Savir, J. Savir, 1983, IEEE Transactions on Computers.

On chip weighted random patterns

Jacob Savir, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Syndrome-Testable Design of Combinational Circuits

Jacob Savir, J. Savir, 1980, IEEE Transactions on Computers.

Coefficient-based test of parametric faults in analog circuits

Jacob Savir, Zhen Guo, 2003, Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412).

On testing safety-sensitive digital systems

Jacob Savir, 2000, Proceedings of the Ninth Asian Test Symposium.

Test limitations of parametric faults in analog circuits

Zhen Guo, Jacob Savir, J. Savir, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Fault Propagation Through Embedded Multiport Memories

Jacob Savir, William H. McAnney, Salvatore R. Vecchio, 1987, IEEE Transactions on Computers.

On shrinking wide compressors

Jacob Savir, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Delay Test Generation: A Hardware Perspective

Jacob Savir, 1997, J. Electron. Test..

Redundancy revisited

Jacob Savir, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Syndrome-Testing of " Syndrome-Untestable" Combinational Circuits

Jacob Savir, J. Savir, 1981, IEEE Transactions on Computers.

Built-In Checking of the Correct Self-Test Signature

Jacob Savir, William H. McAnney, 1988, IEEE Trans. Computers.

BIST diagnostics. I. Simulation models

Jacob Savir, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths

Hideo Fujiwara, Michiko Inoue, Jacob Savir, 2005, IEICE Trans. Inf. Syst..

Generator choices for delay test

Jacob Savir, 1995, Proceedings of the Fourth Asian Test Symposium.

Single-clock, single-latch, scan design

Jacob Savir, A. M. Sheth, 2002, IMTC/2002. Proceedings of the 19th IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.00CH37276).

Reduced Latch Count Shift Registers

Jacob Savir, J. Savir, 1997, J. Electron. Test..

Shrinking wide compressors [BIST]

Jacob Savir, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Scan-based transition test

Srinivas Patil, Jacob Savir, S. Patil, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power-constrained DFT algorithms for non-scan BIST-able RTL data paths

Hideo Fujiwara, Michiko Inoue, Jacob Savir, 2004, 13th Asian Test Symposium.

A New Empirical Test for the Quality of Random Integer Generators

Jacob Savir, 1983, IEEE Transactions on Computers.

Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection

Jacob Savir, J. Savir, 1980, IEEE Transactions on Computers.