Arvind Sudarsanam

发表

Pattern recognition tool to detect reconfigurable patterns in MPEG4 video processing

Ali Akoglu, Aravind Dasu, Arvind Sudarsanam, 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

Memory architecture template for Fast Block Matching algorithms on FPGAs

Aravind Dasu, Arvind Sudarsanam, Shant Chandrakar, 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

Performance of a LU decomposition on a multi-FPGA system compared to a low power commodity microprocessor system

Aravind Dasu, Arvind Sudarsanam, Seth Young, 2007, Scalable Comput. Pract. Exp..

High level-application analysis techniques & architectures - to explore design possibilities for reduced reconfiguration area overheads in FPGAs executing compute intensive applications

Arvind Sudarsanam, Aravind Dasu, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

A novel predicated data flow analysis based memory design for data- and control-intensive multimedia applications

Arvind Sudarsanam, Sethuraman Panchanathan, 2005, IS&T/SPIE Electronic Imaging.

CURRENT TRENDS FOR SILICON AND EMBEDDED COMPUTING SOLUTIONS FOR AUTOMOTIVE APPLICATIONS

Arvind Sudarsanam, Sethuraman Panchanathan, 2002 .

Analysis of Field Programmable Gate Array-Based Kalman Filter Architectures

Arvind Sudarsanam, A. Sudarsanam, 2010 .

Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms

Aravind Dasu, Arvind Sudarsanam, Ramachandra Kallam, 2010, IET Comput. Digit. Tech..

Study of Media Functions on Vector Processing Engines for Network Processing Applications

Chaitali Chakrabarti, Arvind Sudarsanam, Praveen Raghavan, 2004 .

A fast and efficient FPGA-based implementation for solving a system of linear interval equations

Aravind Dasu, Arvind Sudarsanam, 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

A Power Efficient Linear Equation Solver on A Multi-Fpgaaccelerator

Aravind Dasu, Arvind Sudarsanam, Seth Young, 2010 .

Analysis and Design of a Context Adaptable SAD/MSE Architecture

Aravind Dasu, Arvind Sudarsanam, Karthik Vaithianathan, 2009, Int. J. Reconfigurable Comput..

Memory support design for LU decomposition on the starbridge hyper-computer

Aravind Dasu, Arvind Sudarsanam, Seth Young, 2006, 2006 IEEE International Conference on Field Programmable Technology.

PRR-PRR Dynamic Relocation

Aravind Dasu, Arvind Sudarsanam, Ramachandra Kallam, 2009, IEEE Computer Architecture Letters.

Task Scheduling of Control-Data Flow Graphs for Reconfigurable Architectures

Aravind Dasu, Arvind Sudarsanam, Sethuraman Panchanathan, 2004, International Conference on Engineering of Reconfigurable Systems and Algorithms.

Resource estimation and task scheduling for multithreaded reconfigurable architectures

Arvind Sudarsanam, Mayur Srinivasan, Sethuraman Panchanathan, 2004, Proceedings. Tenth International Conference on Parallel and Distributed Systems, 2004. ICPADS 2004..

Multi-FPGA based High Performance LU Decomposition

Arvind Sudarsanam, Thomas Hauser, Seth Young, 2006 .