Daehyun Ahn

OPTIMUS: OPTImized matrix MUltiplication Structure for Transformer neural network accelerator

Jungwook Choi, Junki Park, Jae-Joon Kim, 2020, MLSys.

Time-step interleaved weight reuse for LSTM neural network computing

Jae-Joon Kim, Taesu Kim, Yulhwa Kim, 2020, ISLPED.

Double Viterbi: Weight Encoding for High Compression Ratio and Fast On-Chip Reconstruction for Deep Neural Network

Dongsoo Lee, Jae-Joon Kim, Taesu Kim, 2018, ICLR.

Balancing Computation Loads and Optimizing Input Vector Loading in LSTM Accelerators

Jaeha Kung, Wooseok Yi, Junki Park, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based Pruning

Jae-Joon Kim, Taesu Kim, Daehyun Ahn, 2020, FPGA.

Viterbi-based Pruning for Sparse Matrix with Fixed and High Index Compression Ratio

Dongsoo Lee, Jae-Joon Kim, Taesu Kim, 2018, ICLR.

Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array

Jae-Joon Kim, Hyungjun Kim, Yulhwa Kim, 2018, ISLPED.

Maximizing Parallel Activation of Word-Lines in MRAM-based Binary Neural Network Accelerators

Yulhwa Kim, Hyungjun Kim, Daehyun Ahn, 2021, IEEE Access.

Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS

Yulhwa Kim, Hyungjun Kim, Daehyun Ahn, 2021, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).

SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching

Sungju Ryu, Daehyun Ahn, Jae-Joon Kim, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).