A. Toffoli

发表

Ultra-thin buried nitride integration for multi-VT, low-variability and power management in planar FDSOI CMOSFETs

X. Garros, O. Faynot, F. Andrieu, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

55nm high mobility SiGe(:C) pMOSFETs with HfO/sub 2/ gate dielectric and TiN metal gate for advanced CMOS

F. Andrieu, F. Martin, T. Ernst, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Gate stack solutions in gate-first FDSOI technology to meet high performance, low leakage, VT centering and reliability criteria

X. Garros, J. Mazurier, M. Rafik, 2016, 2016 IEEE Symposium on VLSI Technology.

A novel locally engineered (111) V-channel pMOSFET architecture with improved drivability characteristics for low-standby power (LSTP) CMOS applications

F. Andrieu, T. Ernst, S. Deleonibus, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Reliability of ultra-thin buried oxides for multi-VT FDSOI technology

X. Garros, A. Toffoli, G. Reimbold, 2014 .

Accurate determination of the main parameters from V/sub t/(V/sub b/) curves of fully-depleted SOI devices

O. Faynot, A. Toffoli, B. Giffard, 1995, Proceedings International Conference on Microelectronic Test Structures.

Test structure for characterizing metal thickness in damascene CMP technology

L. Arnaud, A. Toffoli, F. de Crecy, 2008, 2008 IEEE International Conference on Microelectronic Test Structures.

Highly automated sequence for Phase Change Memory test structure characterization

G. Reimbold, B. DeSalvo, J. Cluzel, 2010, 2010 International Conference on Microelectronic Test Structures (ICMTS).

Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization

G. Ghibaudo, J. Cluzel, C. Carabasse, 2014, 2014 IEEE International Electron Devices Meeting.

Analysis of the effect of boron doping on GeTe Phase Change Memories

G. Reimbold, A. Toffoli, L. Perniola, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

O. Faynot, P. Batude, M. Vinet, 2016, 2016 IEEE Symposium on VLSI Technology.

A new Si:C epitaxial channel nMOSFET architecture with improved drivability and short-channel characteristics

T. Ernst, J.-M. Hartmann, S. Deleonibus, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Impact of SET and RESET conditions on CBRAM high temperature data retention

J. Cluzel, E. Vianello, G. Molas, 2014, 2014 IEEE International Reliability Physics Symposium.

Fabrication of a novel strained SiGe:C-channel planar 55 nm nMOSFET for high-performance CMOS

G. Guegan, T. Ernst, J.-M. Hartmann, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

193-nm scanner characterization by SEM and electrical CD measurements

Michel Heitzmann, A. Toffoli, Laurent Pain, 2000, Advanced Lithography.

Investigation of mechanisms shifting metal effective workfunction towards P+ for various Al incorporation scenarii

G. Reimbold, G. Ghibaudo, C. Leroux, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Phase Change Memory advanced electrical characterization for conventional and alternative applications

G. Reimbold, B. DeSalvo, A. Toffoli, 2012, 2012 IEEE International Conference on Microelectronic Test Structures.

Resistive Memories for Ultra-Low-Power embedded computing design

B. Giraud, M. Alayan, E. Vianello, 2014, 2014 IEEE International Electron Devices Meeting.

Guidance to reliability improvement in CBRAM using advanced KMC modelling

C. Carabasse, G. Molas, M. Bernard, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories

G. Ghibaudo, D. Lafond, S. Deleonibus, 2011, 2011 International Electron Devices Meeting.

Planar Double Gate CMOS transistors with 40nm metal gate for multipurpose applications

Sylvain Maitrejean, Yves Morand, Maud Vinet, 2004 .

Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length

O. Faynot, P. Batude, M. Vinet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Carbon-doped GeTe Phase-Change Memory featuring remarkable RESET current reduction

G. Reimbold, D. Blachier, A. Toffoli, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications

T. Ernst, S. Deleonibus, T. Skotnicki, 2007, 2007 IEEE International Electron Devices Meeting.

Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

O. Faynot, G. Ghibaudo, F. Andrieu, 2006, 2006 International Electron Devices Meeting.

Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length

J. Mazurier, O. Faynot, G. Ghibaudo, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Investigation of HfO2/Ti based vertical RRAM - Performances and variability

G. Ghibaudo, J. Cluzel, P. Brianceau, 2014, 2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS).

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

X. Garros, O. Faynot, F. Andrieu, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

How far will silicon nanocrystals push the scaling limits of NVMs technologies?

G. Ghibaudo, D. Ielmini, S. Deleonibus, 2003, IEEE International Electron Devices Meeting 2003.

Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length

X. Garros, J. Mazurier, O. Faynot, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length

O. Rozeau, O. Faynot, M. Vinet, 2014, 2014 IEEE International Electron Devices Meeting.

SiGe channel p-MOSFETs scaling-down

G. Ghibaudo, F. Andrieu, T. Ernst, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories

X. Garros, S. Deleonibus, Gerard Ghibaudo, 2009, ESSDERC 2009.

Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX

X. Garros, J. Mazurier, O. Rozeau, 2010, 2010 International Electron Devices Meeting.

Atomistic mechanisms of copper filament formation and composition in Al2O3-based conductive bridge random access memory

G. Molas, M. Bernard, A. Toffoli, 2017 .

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

X. Garros, O. Faynot, Yves Campidelli, 2007 .

Single electron effects and structural effects in ultrascaled silicon nanocrystal floating-gate memories

G. Ghibaudo, S. Deleonibus, G. Molas, 2004, IEEE Transactions on Nanotechnology.

FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)

O. Faynot, P. Batude, S. Cristoloveanu, 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS).

Automatic full quantum analysis of CV measurements for bulk and SOI devices

G. Reimbold, Gerard Ghibaudo, A. Toffoli, 2011 .

/spl Omega/FETs transistors with TiN metal gate and HfO/sub 2/ down to 10nm

X. Garros, O. Faynot, M. Vinet, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Investigation on TSV impact on 65nm CMOS devices and circuits

J. Cluzel, A. Toffoli, G. Haury, 2010, 2010 International Electron Devices Meeting.

On Carbon doping to improve GeTe-based Phase-Change Memory data retention at high temperature

G. Reimbold, D. Blachier, A. Toffoli, 2010, 2010 IEEE International Memory Workshop.

Lowering the Reset Current and Power Consumption of Phase-Change Memories with Carbon-Doped Ge2Sb2Te5

G. Reimbold, P. Zuliani, G. Pananakakis, 2012, 2012 4th IEEE International Memory Workshop.

N-doped GeTe as performance booster for embedded Phase-Change Memories

G. Reimbold, D. Blachier, A. Toffoli, 2010, 2010 International Electron Devices Meeting.

GeOI and SOI 3D monolithic cell integrations for high density applications

X. Garros, O. Rozeau, O. Faynot, 2006, 2009 Symposium on VLSI Technology.

Electrical Performances of Tellurium-Rich GexTe1-x Phase Change Memories

P. Zuliani, G. Navarro, A. Toffoli, 2011, 2011 3rd IEEE International Memory Workshop (IMW).

High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration

X. Garros, G. Ghibaudo, M.-P. Samson, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Investigating doping effects on high-κ metal gate stack for effective work function engineering

G. Reimbold, Pierre Caubet, Gerard Ghibaudo, 2013 .

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

O. Rozeau, O. Faynot, M. Vinet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Analysis by simulation of amorphization current in phase change memory applied to pillar and GST confined type cells

Sylvain Maitrejean, A. Toffoli, L. Perniola, 2011 .

Electrical Performance of High Density 10 µm Diameter 20 µm Pitch Cu-Pillar with Chip to Wafer Assembly

L. Arnaud, R. Franiatte, A. Toffoli, 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).