J. Dechamp

Ultra-thin buried nitride integration for multi-VT, low-variability and power management in planar FDSOI CMOSFETs

X. Garros, O. Faynot, F. Andrieu, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Germanium-on-insulator (GeOI) structures realized by the Smart Cut/spl trade/ technology

C. Mazure, N. Kernevez, C. Morales, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Recent developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking

J. Dechamp, L. Clavelier, F. Letertre, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

Transfer of patterned Si and SiO/sub 2/ layers for the fabrication of patterned and mixed SOI

B. Ghyselen, C. Mazure, N. Kernevez, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Towards a Complete Direct Hybrid Bonding D2W Integration Flow: Known-Good-Dies and Die Planarization Modules Development

M. Zussy, J. Dechamp, A. Jouve, 2019, 2019 International 3D Systems Integration Conference (3DIC).

First demonstration of heat dissipation improvement in CMOS technology using Silicon-On-Diamond (SOD) substrates

O. Faynot, F. Andrieu, S. Deleonibus, 2009, 2009 IEEE International SOI Conference.

Transfers of 2-inch GaN films onto sapphire substrates using Smart Cut/sup TM/ technology

N. Kernevez, M. Zussy, J. Dechamp, 2005 .

Chip-to-chip interconnections based on the wireless capacitive coupling for 3D integration

Roberto Guerrieri, M. Zussy, Roberto Canegallo, 2006 .

Investigation of stress induced voiding and electromigration phenomena on direct copper bonding interconnects for 3D integration

L. Di Cioccio, J. Dechamp, R. Fortunier, 2011, 2011 International Electron Devices Meeting.