G. Coussens

An experimental 295 MHz CMOS 4K/spl times/256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers

Natsuki Kushiyama, C. Tan, R. Clark, 1995 .

A 295 MHz CMOS 1 M (/spl times/256) embedded SRAM using bi-directional read/write shared sense amps and self-timed pulsed word-line drivers

Natsuki Kushiyama, R. Clark, L. Martin, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.