M. Kawano

PRD-based global-mean-time signaling for high-speed chip-to-chip communications

H. Tamura, M. Taguchi, H. Araki, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

SMAFTI packaging technology for new interconnect hierarchy

K. Masu, S. Amakawa, M. Kawano, 2009, 2009 IEEE International Interconnect Technology Conference.

Ka-band low loss and high power handling GaAs PIN diode MMIC phase shifter for reflected-type phased array systems

M. Kawano, H. Takasu, S. Kamihashi, 1999, 1999 IEEE MTT-S International Microwave Symposium Digest (Cat. No.99CH36282).

A 256 Mb SDRAM using a register-controlled digital DLL

Y. Serizawa, M. Taguchi, K. Nishimura, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

N. Takahashi, K. Soejima, M. Kawano, 2009, IEEE Transactions on Advanced Packaging.

A 3D Packaging Technology for High-Density Stacked DRAM

M. Kawano, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Reliability studies of Sn-Ag-Cu BGA solder joints on Ni/Cu/Au surface finish for SMAFTI packaging technology

K. Soejima, M. Kawano, M. Kawano, 2008, 2008 58th Electronic Components and Technology Conference.

A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

K. Soejima, M. Kawano, N. Takahashi, 2006, 2006 International Electron Devices Meeting.

A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology

K. Soejima, M. Kawano, N. Takahashi, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

A novel "SMAFTI" package for inter-chip wide-band data transfer

M. Tago, K. Soejima, M. Kawano, 2006, 56th Electronic Components and Technology Conference 2006.