Shang-Wei Tu

Inductance Modeling for On-Chip Interconnects

Jing-Yang Jou, Wen-Zen Shen, Shang-Wei Tu, 2002 .

Layout techniques for on-chip interconnect inductance reduction

Yao-Wen Chang, Jing-Yang Jou, Shang-Wei Tu, 2004 .

On-Chip Bus Encoding for Power Minimization Under Delay Constraint

Jing-Yang Jou, Shang-Wei Tu, Tzu-Wei Lin, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction

Yao-Wen Chang, Jing-Yang Jou, Shang-Wei Tu, 2005, 2005 IEEE International Symposium on Circuits and Systems.

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction

Yao-Wen Chang, Jing-Yang Jou, Shang-Wei Tu, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

RLC effects on worst-case switching pattern for on-chip buses

Yao-Wen Chang, Jing-Yang Jou, Shang-Wei Tu, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

On-chip bus encoding for LC cross-talk reduction

Jing-Yang Jou, Shang-Wei Tu, Jiun-Sheng Huang, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

Layout techniques for on-chip interconnect inductance reduction

Yao-Wen Chang, Jing-Yang Jou, Shang-Wei Tu, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).