David L. Landis

发表

Language-based rapid prototyping methods for legacy system re-engineering and re-use

David L. Landis, Praveen Guddeti, Paul T. Hulina, 1999, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246).

A test methodology for wafer scale system

David L. Landis, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Wafer-scale optimization using computational availability

Joseph W. Yoder, David L. Landis, Nitin Nigam, 1992, Computer.

A rapid prototyping methodology for reverse engineering of legacy electronic systems

David L. Landis, Paul T. Hulina, Sanjay Balasubramanian, 1999, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246).

A WWW facilitated rapid system prototyping class

David L. Landis, Paul T. Hulina, 1997, Proceedings of International Conference on Microelectronic Systems Education.

Test Generation for Precise Interrupts on Out-of-Order Microprocessors

Narayanan Vijaykrishnan, David L. Landis, Padmaraj Singh, 2009, 2009 10th International Workshop on Microprocessor Test and Verification.

WSI implementation of an 8-point FFT

H. A. Nienhaus, David L. Landis, 1990, IEEE Proceedings on Southeastcon.

Test Generation for CMP Designs

David L. Landis, Padmaraj Singh, 2010, 2010 11th International Workshop on Microprocessor Test and Verification.

The sandbox design experience course

Narayanan Vijaykrishnan, David L. Landis, Ivan S. Kourtev, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

An electronics manufacturing minor in engineering with emphasis on rapid prototyping

David L. Landis, Paul T. Hulina, 1997, Proceedings of International Conference on Microelectronic Systems Education.

Using RASSP modules in a rapid system prototyping class

David L. Landis, 1999, Proceedings 1999 IEEE International Conference on Microelectronic Systems Education (MSE'99) 'Systems Education in the 21st Century' (Cat. No.99-63794).

Influence of Built-In Self Test on the Performance of Fault Tolerant VLSI Multiprocessors

David L. Landis, William A. Check, Daniel C. Muha, 1987, ICPP.

Evaluation of computing in memory architectures for digital image processing applications

David L. Landis, Paul T. Hulina, Lee D. Coraor, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Microelectronics education as workforce development

James T. Cain, David L. Landis, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits

David L. Landis, Sami A. Al-Arian, Bassam Shaer, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Wafer Scale Integration: A university perspective

Vijay K. Jain, David L. Landis, David C. Keezer, 1991, J. VLSI Signal Process..

Pseudo-exhaustive testing of sequential circuits

David L. Landis, Sami A. Al-Arian, Bassam Shaer, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Partitioning algorithm to enhance VLSI testability

David L. Landis, Sami A. Al-Arian, Bassam Shaer, 1998, ACM-SE 36.

Hazard driven test generation for SMT processors

Narayanan Vijaykrishnan, David L. Landis, Padmaraj Singh, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Partitioning sequential circuits for pseudoexhaustive testing

David L. Landis, Sami A. Al-Arian, Bassam Shaer, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Short Courses in System-on-a-Chip (SoC) design

Donald M. Chiarulli, Steven P. Levitan, Bruce R. Childers, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

Targeted random test generation for power-aware multicore designs

Narayanan Vijaykrishnan, David L. Landis, Padmaraj Singh, 2012, TODE.

Evaluation of system BIST using computational performance measures

David L. Landis, Daniel C. Muha, D. Landis, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

Computing in memory architectures for digital image processing

David L. Landis, Paul T. Hulina, Lee D. Coraor, 1999, Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing.

A self-test system architecture for reconfigurable WSI

David L. Landis, 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs

David L. Landis, Sami A. Al-Arian, Stephan P. Athan, 1996, Proceedings of 14th VLSI Test Symposium.

Applications of the IEEE P1149.5 module test and maintenance bus

David L. Landis, Patrick F. McHugh, Chuck Hudson, 1992, Proceedings International Test Conference 1992.

Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration

David L. Landis, Padmaraj Singh, 1990, Proceedings. International Test Conference 1990.