Paul T. Hulina

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Language-based rapid prototyping methods for legacy system re-engineering and re-use

David L. Landis, Praveen Guddeti, Paul T. Hulina, 1999, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246).

A rapid prototyping methodology for reverse engineering of legacy electronic systems

David L. Landis, Paul T. Hulina, Sanjay Balasubramanian, 1999, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246).

A Hardware Memory Mapping Unit for Efficient Address Computation

Paul T. Hulina, Lee D. Coraor, 1987, ICPP.

Memory Latency Effects in Decoupled Architectures

Lizy Kurian John, Paul T. Hulina, Lee D. Coraor, 1994, IEEE Trans. Computers.

Classification and Performance Evaluation of Instruction Buffering Techniques

Lizy Kurian John, Paul T. Hulina, Lee D. Coraor, 1991, ISCA.

A WWW facilitated rapid system prototyping class

David L. Landis, Paul T. Hulina, 1997, Proceedings of International Conference on Microelectronic Systems Education.

Microprocessors: The Key to Cost-Effective Instrumentation

Paul T. Hulina, David R. Voltmer, 1981, IEEE Transactions on Education.

An electronics manufacturing minor in engineering with emphasis on rapid prototyping

David L. Landis, Paul T. Hulina, 1997, Proceedings of International Conference on Microelectronic Systems Education.

Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits

Paul T. Hulina, Jon G. Bredeson, 1972, Inf. Control..

Memory latency effects in decoupled architectures with a single data memory module

Paul T. Hulina, Lee D. Coraor, Lizyamma Kurian, 1992, ISCA '92.

A comparative evaluation of software techniques to hide memory latency

Lizy Kurian John, Paul T. Hulina, Lee D. Coraor, 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

A Reconfigurable Multiprocessor

Paul T. Hulina, Lee D. Coraor, 1985, ICPP.

Coprocessor architectures for efficient address computation and memory accessing

Paul T. Hulina, Lee D. Coraor, 1990, Comput. Syst. Sci. Eng..

Evaluation of computing in memory architectures for digital image processing applications

David L. Landis, Paul T. Hulina, Lee D. Coraor, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Program balance and its impact on high performance RISC architectures

Lizy Kurian John, Paul T. Hulina, Lee D. Coraor, 1995, Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture.

Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races

Paul T. Hulina, Jon G. Bredeson, 1971, IEEE Transactions on Computers.

Specification of a coprocessor for efficient access of data structures

Paul T. Hulina, Lee D. Coraor, A. S. Berrached, 1992, Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences.

Generation of Prime Implicants by Direct Multiplication

Paul T. Hulina, Jon G. Bredeson, 1971, IEEE Transactions on Computers.

Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops

Paul T. Hulina, Jon G. Bredeson, 1973, IEEE Transactions on Computers.

A decoupled access/execute architecture for efficient access of structured data

Paul T. Hulina, Lee D. Coraor, Ali Berrached, 1993, [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences.

Structured Data Access Mechanisms for a Decoupled Computer Architecture

Paul T. Hulina, Lee D. Coraor, Ali Berrached, 1994, 1994 Internatonal Conference on Parallel Processing Vol. 2.

The binary floating point digital differential analyzer

Paul T. Hulina, James L. Elshoff, 1970, AFIPS '70 (Fall).

Computing in memory architectures for digital image processing

David L. Landis, Paul T. Hulina, Lee D. Coraor, 1999, Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing.

Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits

Paul T. Hulina, Jon G. Bredeson, 1970, SWAT.

Performance Analysis of an Address Generation Coprocessor

Paul T. Hulina, Lee D. Coraor, Shih-Wei Sun, 1991, ICPP.

On Tracey's Internal State Assignment Method

Paul T. Hulina, Jon G. Bredeson, 1970, IEEE Transactions on Computers.

Classification and performance evaluation of instruction buffering techniques

Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai, 1991, [1991] Proceedings. The 18th Annual International Symposium on Computer Architecture.

Memory Latency Effects in Decoupled Architectures with a Single Data Memory Module

Lizy Kurian John, Paul T. Hulina, Lee D. Coraor, 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.

Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories

Lizy Kurian John, Paul T. Hulina, Lee D. Coraor, 1994, 1994 International Conference on Parallel Processing Vol. 1.

Design and VLSI implementation of an address generation coprocessor

Paul T. Hulina, Lee D. Coraor, Eugene John, 1995 .

A General Model for Memory-Based Finite-State Machines

Paul T. Hulina, Lee D. Coraor, Orlando A. Morean, 1987, IEEE Transactions on Computers.

Memory Latency E ects in Decoupled ArchitecturesLizyamma

Paul T. Hulina, Kurian, D. Lee, 1994 .