Togawa Nozomu

发表

Hash-table and Balanced-tree based FIB Architecture for CCN Routers Reducing Memory Accesses

Shimazaki Kenta, Aoki Takashi, Hatano Takahiro, 2015 .

SIMD Instructions Generation Algorithm for Multiple Loop for SIMD Processor Cores Optimum Design

Togawa Nozomu, Nakajima Hiroki, Kohara Shunitsu, 2007 .

Scan-based Attack on the LED Block Cipher Using Scan Signatures

Togawa Nozomu, Yanagisawa Masao, Fujishiro Mika, 2013 .

A Deformed Map Generation Algorithm Considering Visibility in a Small Size Display and Easiness of Route Understanding for Pedestrian Navigation

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2006 .

A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs

Togawa Nozomu, Yanagisawa Masao, Fujiwara Koichi, 2014 .

Changing Organization through Continuous Data Collection with Business Microscope

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2010 .

Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2010 .

A routing selection method for improving the response time in anycast communications

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2007 .

A Pedestrian Positioning System Using Road Traffic Signs and Landmarks Based on Current Location Recognition

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2010 .

An aging aware high-level synthesis algorithm with floorplanning

Togawa Nozomu, Yanagisawa Masao, Igawa Koki, 2016 .

Positioning Method Using Road Traffic Sign to Correct GPS Error for Pedestrian Navigation

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2007 .

A floorplan-driven high-level synthesis algorithm for reducing multiplexer inputs targeting FPGAs

Togawa Nozomu, Yanagisawa Masao, Fujiwara Koichi, 2014 .

Local pulse generation in variable stages pipeline designs for low energy consumption

Togawa Nozomu, Yanagisawa Masao, Nii Takayuki, 2014 .

Design and Evalution of a Butterfly Circuit Using Selector Logic by Bit-Level Transformation

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2010 .

Hardware Trojan Identification based on Netlist Features using Neural Networks

Togawa Nozomu, Yanagisawa Masao, Hasegawa Kento, 2016 .

Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures

Togawa Nozomu, Yanagisawa Masao, Abe Shin-ya, 2012 .

An Application Specific Data Optimization System for Processor Cores and Its Experimental Evaluation

Togawa Nozomu, Kohara Shunitsu, Yanagisawa Masao, 2007 .

A route selection method based on router loads in anycast communications

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

A low-power soft error tolerant latch scheme

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2015 .

Malisious tamper detector design with capacitance measurement for IoT devices in operation

Togawa Nozomu, Yanagisawa Masao, Takenaka Takashi, 2016 .

A Quantitative Criterion of Gate-Level Netlist Vulnerability

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2015 .

Evaluation of Rotator-based Multiplexer Network with Control Circuits for Field-data Extractors

Togawa Nozomu, Yanagisawa Masao, Kawamura Kazushi, 2016 .

A Design Technique for Approximate Circuits based on Artificial Neural Network

Togawa Nozomu, Yanagisawa Masao, Kawamura Kazushi, 2017 .

A Forwarding Unit Optimization Method for Application Processors

Togawa Nozomu, Kohara Shunitsu, Yanagisawa Masao, 2006 .

Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures (Preprint)

Togawa Nozomu, Yanagisawa Masao, Kodera Hirokazu, 2013 .

Secure Scan Architecture Using State Dependent Scan Flip Flop with Key-Based Configuration against Scan-Based Attack

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2012 .

An Implementation of dynamically reconfigurable multi-rate compatible LDPC decoder

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2006 .

Secure scan design using improved random order scans and its evaluations

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2014 .

A Processing Unit Optimization Algorithm in SIMD Processor Cores Design

Togawa Nozomu, Kohara Shunitsu, Yanagisawa Masao, 2007 .

A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA

Togawa Nozomu, Yanagisawa Masao, Kawamura Kazushi, 2015 .

A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures

Togawa Nozomu, Yanagisawa Masao, Terada Kotaro, 2016 .

A DFG Mapping Algorithm for Flexible Engine/Generic ALU Array

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

CoDaMa: An XML-based Framework for Manipulating CDFGs

Togawa Nozomu, Kohara Shunitsu, Yanagisawa Masao, 2007 .

High speed design of sub-threshold circuit by using DTMOS

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2014 .

Positioning Method Using Camera Phone and Landmark for Pedestrian Navigation

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2007 .

An Energy-efficent ASIP Synthesis Method Based on Reducing Bit-width of Instruction Memory

Togawa Nozomu, Kohara Shunitsu, Yanagisawa Masao, 2008 .

Filter Design for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2007 .

Performance comparison of integer encoding methods in Ising machines

Togawa Nozomu, Tanaka Shu, Tamura Kensuke, 2020 .

連続してハッシュ値を出力しないHMAC‐SHA‐256回路へのスキャンベース攻撃手法

Togawa Nozomu, Yanagisawa Masao, Oku Daisuke, 2017 .

SAAV : Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages

Togawa Nozomu, Yanagisawa Masao, Abe Shin-ya, 2012 .

User's Route Preference Investigation in Indoor Environment and Its Associative Route Searching Method

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

A Field Data Extractor Configuration Based on Multiplexer Tree Partitioning

Togawa Nozomu, Yanagisawa Masao, Kawamura Kazushi, 2014 .

A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2009 .

Secure Scan Architecture on RSA Circuit Using State Dependent Scan Flip Flop against Scan-Based Side Channel Attack

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2012 .

Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories

Togawa Nozomu, Yanagisawa Masao, Kimura Shinji, 2014 .

Demonstration of Adversarial Examples for Hardware Trojan Detection

Hashimoto Kazuo, Togawa Nozomu, Hasegawa Kento, 2019 .

A Hybrid Routing Protocol Using Location Information for Mobile Ad Hoc Networks

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2014 .

High-Level Synthesis with Floorplan for GDR Architectures and its Evaluation

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2010 .

High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit for IEEE 802.11n Standard

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2009 .

A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures

Togawa Nozomu, Yanagisawa Masao, Kawamura Kazushi, 2013 .

Timing-error-tolerant AES Cipher

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2016 .

An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2014 .

A fast handoff method with reducing latency and packet loss for mobile communications

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

Connectivity-based and Load-balanced Cluster Routing for Mobile Ad hoc Networks

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2010 .

FPGA Design and Evaluation of Selector-Logic-based Butterfly Unit

Togawa Nozomu, Yanagisawa Masao, Ito Koki, 2016 .

A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access

Kobayashi Yuta, Togawa Nozomu, Yanagisawa Masao, 2009 .

A Hardware Trojan Detection Method based on Trojan net features

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2015 .

Area/delay Estimation for Application Processor

Togawa Nozomu, Kohara Shunitsu, Yanagisawa Masao, 2006 .

Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits

Togawa Nozomu, Yanagisawa Masao, Abe Shin-ya, 2014 .

Super-resolution by UsingWeighted Adders with Selector Logics

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2011 .

An Evaluation Method of Road Illuminance Levels Using Road Lights and Landmarks

Togawa Nozomu, Yanagisawa Masao, Bao Siya, 2017 .

A Parallel Hardware Engine for Generating Deformed Maps

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

Accuracy Evaluation of Trace-based Cache Simulation for Two-core L1 Caches

Togawa Nozomu, Yanagisawa Masao, Tawada Masashi, 2013 .

DFG Mapping for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2009 .

The role of System and Signal Processing Subsociety -- Offering Effective Information of Research Groups and The Subsociety

Takai Shigemasa, Aikawa Naoyuki, Togawa Nozomu, 2019 .

Scan-based Attack against Camellia Cryptosystems

Togawa Nozomu, Yanagisawa Masao, Kodera Hirokazu, 2012 .

An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2011 .

Theory of Ising Machines and a Common Software Platform for Ising Machines

Togawa Nozomu, Tanaka Shu, Matsuda Yoshiki, 2020 .

A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures

Togawa Nozomu, Yanagisawa Masao, Igawa Koki, 2014 .

A Clustering Technique for Energy Consumption Reduction in Wireless Sensor Network

Togawa Nozomu, Kohara Shunitsu, Yanagisawa Masao, 2007 .

Radix-2 Butterfly Circuit Architecture Using Selector Logic

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

A non-volatile memory writing reduction method based on state encoding limiting maximum Hamming distance

Togawa Nozomu, Yanagisawa Masao, Kimura Shinji, 2013 .

A Functional Unit Design of Motion Estimator on DSP for H.264/AVC Encoding

Togawa Nozomu, Kohara Shunitsu, Yanagisawa Masao, 2006 .

A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2015 .

Hardware Trojan Identification based on Netlist Features using SVM

Togawa Nozomu, Yanagisawa Masao, Hasegawa Kento, 2015 .

Fast Interconnect Delay Estimation with Considering Inductance Based on Multiple Regression Analysis

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2005 .

FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis

Togawa Nozomu, Yanagisawa Masao, Kazushi Kawamura, 2016 .

A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs

Togawa Nozomu, Yanagisawa Masao, Fujiwara Koichi, 2015 .

AES Encryption Circuit against Clock Glitch based Fault Analysis

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2015 .

A pipeline architecture optimization algorithm for SIMD-type processor core synthesis

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2006 .

Finite state machine design for high accurate stochastic computing

Togawa Nozomu, Yanagisawa Masao, Tawada Masashi, 2017 .

A Destination Speculating System Considering Individual Preferences and Congestions for Indoor Pedestrian Navigation

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2006 .

An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead

Togawa Nozomu, Yanagisawa Masao, Kawamura Kazushi, 2013 .

A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations

Togawa Nozomu, Yanagisawa Masao, Igawa Koki, 2016 .

Write-Reduction using Encoding data on MLC for Non-Volatile Memories

Togawa Nozomu, Yanagisawa Masao, Kimura Shinji, 2016 .

A Consideration of MPEG-A Photo Player Meta-data Generation System Design with Hardware Acceleration for Mobile Devices

Togawa Nozomu, Kohara Shunitsu, Yanagisawa Masao, 2007 .

A Load-Balancing Anycast Route Selection Method for Reducing Control Packets

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

Partitioned Hash-table and Balanced-tree based FIB Architecture

Nakazato Hidenori, Shimazaki Kenta, Miyazaki Akihiko, 2016 .

Multicast routing protocol with collision avoidance in multi-group wireless ad-hoc networks

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2010 .

Evaluation of energy consumption for two-level cache using Non-Volatile Memory for IL1 and UL2 caches

Togawa Nozomu, Yanagisawa Masao, Kimura Shinji, 2013 .

Verification Experiment of Scan-based Attack against a Trivium Cipher Circut

Togawa Nozomu, Yanagisawa Masao, Oku Daisuke, 2016 .

An Elliptic Area Search Algorithm Based on a Mobile User Destination

Yamamoto Takayuki, Togawa Nozomu, Yanagisawa Masao, 2007 .

Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2011 .

Design of Flip-Flop with Timing Error Tolerance

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2014 .

Scan-based Attack against Trivium Stream Cipher Using Scan Signatures

Togawa Nozomu, Yanagisawa Masao, Fujishiro Mika, 2013 .

Scan-based Attack against Triple DES Cryptosystems Using Scan Signatures

Togawa Nozomu, Yanagisawa Masao, Kodera Hirokazu, 2011 .

Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture

Togawa Nozomu, Yanagisawa Masao, Abe Shin-ya, 2013 .

A fast handoff method by using NEMO for high-speed mobile terminal

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

In-situ Hardware-Trojan Authentication for Invalidating Malicious Functions

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2016 .

A Route Searching Algorithm Based on Individual Preference for Indoor Pedestrian Navigation

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2006 .

Scan-based Attack for an AES-LSI included with other IPs

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages

Togawa Nozomu, Yanagisawa Masao, Abe Shin-ya, 2014 .

A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems

Aoki Takashi, Togawa Nozomu, Nakanishi Mamoru, 2014 .

Positional System Using Traffic Sign for Pedestrian Navigation System

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2006 .

A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories

Togawa Nozomu, Yanagisawa Masao, Kimura Shinji, 2015 .

Multi-Rate Compatible High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .

A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories

Togawa Nozomu, Yanagisawa Masao, Kimura Shinji, 2015 .

Latch-based AES Encryption Circuit Against Fault Analysis

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2014 .

A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures

Togawa Nozomu, Yanagisawa Masao, Hagio Yuta, 2014 .

Energy Evaluation of Writing Reduction Method for Non-Volatile Memory

Togawa Nozomu, Yanagisawa Masao, Kimura Shinji, 2013 .