J.D. Hibbeler

Moving Carefully Towards Model-based Layout Optimization and Checking

J.D. Hibbeler, D.N. Maynard, 2007, 2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.

Measurement and reduction of critical area using Voronoi diagrams

J.D. Hibbeler, D.N. Maynard, 2005, IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing 2005..