Mohammad Hosseinabady

发表

IEEE International High Level Design Validation and Test Workshop (HLDVT) (to appear)

Jimson Mathew, Mohammad Hosseinabady, M. Reza, 2007 .

Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation

Mohammad Hosseinabady, José Luis Núñez-Yáñez, 2012, IET Comput. Digit. Tech..

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC

Alfredo Benso, Giorgio Di Natale, Paolo Prinetto, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA

Rafael Asenjo, Mohammad Hosseinabady, Angeles G. Navarro, 2018, The Journal of Supercomputing.

Run-time resource management in fault-tolerant network on reconfigurable chips

Mohammad Hosseinabady, José L. Núñez-Yáñez, 2009, 2009 International Conference on Field Programmable Logic and Applications.

Single Event Upset Detection and Correction

Dhiraj K. Pradhan, Jimson Mathew, Jawar Singh, 2007, 10th International Conference on Information Technology (ICIT 2007).

Exploring dynamically reconfigurable multicore designs with NoRC designer

Mohammad Hosseinabady, José L. Núñez-Yáñez, Arash Beldachi, 2012, 2012 International Conference on High Performance Computing & Simulation (HPCS).

A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis

Mohammad Hosseinabady, Jose L Nunez-Yanez, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities pdf

Mohammad Hosseinabady, José Núñez-Yáñez, Mohd Amiruddin Bin Zainol, 2019, ArXiv.

Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling

Mohammad Hosseinabady, Jose Nunez-Yanez, Kris Nikov, 2020, PARMA-DITAM@HiPEAC.

Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles

Mohammad Hosseinabady, José Luis Núñez-Yáñez, 2012, IET Comput. Digit. Tech..

Fault-Tolerant Reconfigurable On-Chip-Network

Mohammad Hosseinabady, Jose L Nunez-Yanez, 2014 .

Single Event Upset Detection and Correction

Dhiraj K. Pradhan, Jimson Mathew, Jawar Singh, 2007 .

Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC

Jose L Nunez-Yanez, Arash Farhadi Beldachi, Mohammad Hosseinabady, 2013 .

Task Dispersal Measurement in Dynamic Reconfigurable NoCs

Mohammad Hosseinabady, José Luis Núñez-Yáñez, Antonio Marcello Coppola, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Using the Inter- and Intra-Switch Regularity in NoC Switch Testing

Zainalabedin Navabi, Mohammad Hosseinabady, Atefe Dalirsani, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Single-Event Upset Analysis and Protection in High Speed Circuits

Alfredo Benso, Giorgio Di Natale, Paolo Prinetto, 2006, Eleventh IEEE European Test Symposium (ETS'06).

A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis

Mohammad Hosseinabady, José Luis Núñez-Yáñez, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Reducing test power, time and data volume in SoC testing using selective trigger scan architecture

Zainalabedin Navabi, Mohammad Hosseinabady, Shervin Sharifi, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System

Mohammad Hosseinabady, Jose Nunez-Yanez, J. Núñez-Yáñez, 2020, PARMA-DITAM@HiPEAC.

Reliable network-on-chip based on generalized de Bruijn graph

Dhiraj K. Pradhan, Jimson Mathew, Mohammad Reza Kakoee, 2007, 2007 IEEE International High Level Design Validation and Test Workshop.

Fault tolerant bit parallel finite field multipliers using LDPC codes

Dhiraj K. Pradhan, Jimson Mathew, Jawar Singh, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Simultaneous reduction of dynamic and static power in scan structures

Ali Afzali-Kusha, Zainalabedin Navabi, Mohammad Hosseinabady, 2005, Design, Automation and Test in Europe.

Low overhead DFT using CDFG by modifying controller

Fabrizio Lombardi, Zainalabedin Navabi, Mohammad Hosseinabady, 2007, IET Comput. Digit. Tech..

Pipelined Streaming Computation of Histogram in FPGA OpenCL

Mohammad Hosseinabady, José Luis Núñez-Yáñez, 2017, PARCO.

Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip

Rafael Asenjo, Mohammad Hosseinabady, José L. Núñez-Yáñez, 2017, PARCO.

Dynamic Energy Management of FPGA Accelerators in Embedded Systems

Mohammad Hosseinabady, José Luis Núñez-Yáñez, 2018, TECS.

Fault-tolerant dynamically reconfigurable NoC-based SoC

Mohammad Hosseinabady, José L. Núñez-Yáñez, 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.

Low test application time resource binding for behavioral synthesis

Zainalabedin Navabi, Mohammad Hosseinabady, Pejman Lotfi-Kamran, 2007, TODE.

Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems pdf

Rafael Asenjo, Mohammad Hosseinabady, José L. Núñez-Yáñez, 2018, ArXiv.

Effective modelling of large NoCs using SystemC

Mohammad Hosseinabady, José L. Núñez-Yáñez, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs

Dhiraj K. Pradhan, Jimson Mathew, Mohammad Reza Kakoee, 2008, 2008 Design, Automation and Test in Europe.

Simultaneous multiprocessing in a software-defined heterogeneous FPGA

Rafael Asenjo, Mohammad Hosseinabady, Angeles G. Navarro, 2018, The Journal of Supercomputing.

A Selective Trigger Scan Architecture for VLSI Testing

Fabrizio Lombardi, Zainalabedin Navabi, Mohammad Hosseinabady, 2008, IEEE Transactions on Computers.

SystemC Architectural Transaction Level Modelling for Large NoCs

Mohammad Hosseinabady, José L. Núñez-Yáñez, 2010, FDL.

Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

Mohammad Hosseinabady, José Luis Núñez-Yáñez, Arash Beldachi, 2016, IEEE Transactions on Computers.

A concurrent testing method for NoC switches

Zainalabedin Navabi, Mohammad Hosseinabady, Mahdi Nazm Bojnordi, 2006, Proceedings of the Design Automation & Test in Europe Conference.

An Analytical Model for Reliability Evaluation of NoC Architectures

Zainalabedin Navabi, Mohammad Hosseinabady, Atefe Dalirsani, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip pdf

Rafael Asenjo, Mohammad Hosseinabady, José L. Núñez-Yáñez, 2020, ArXiv.

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices

Mohammad Hosseinabady, José Luis Núñez-Yáñez, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

Single-Event Transient Analysis in High Speed Circuits

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2011, 2011 International Symposium on Electronic System Design.

Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing

Zainalabedin Navabi, Mohammad Hosseinabady, Shervin Sharifi, 2003, VLSI-SOC.

A UML Based System Level Failure Rate Assessment Technique for SoC Designs

Zainalabedin Navabi, Mohammad Hosseinabady, Mohammad Hossein Neishaburi, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Energy optimization of FPGA-based stream-oriented computing with power gating

Mohammad Hosseinabady, José Luis Núñez-Yáñez, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

Application of de Bruijn graphs to NoC design

Jimson Mathew, Mohammad Hosseinabady, Pradhan Dhiraj, 2007 .

Scan-Based Structure with Reduced Static and Dynamic Power Consumption

Ali Afzali-Kusha, Zainalabedin Navabi, Mohammad Hosseinabady, 2006, J. Low Power Electron..

Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph

Dhiraj K. Pradhan, Jimson Mathew, Mohammad Reza Kakoee, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes

Mohammad Hosseinabady, José L. Núñez-Yáñez, Atukem Nabina, 2009, 2009 IEEE Control Applications, (CCA) & Intelligent Control, (ISIC).

A Flow Graph Technique for DFT Controller Modification

Fabrizio Lombardi, Mohammad Hosseinabady, Pejman Lotfi-Kamran, 2005, Proceedings 2005 IEEE International SOC Conference.

TED+: a data structure for microprocessor verification

Zainalabedin Navabi, Mohammad Hosseinabady, Mehran Massoumi, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Multi-precision convolutional neural networks on heterogeneous hardware

Simon McIntosh-Smith, Mohammad Hosseinabady, José L. Núñez-Yáñez, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Run-time power gating in hybrid ARM-FPGA devices

Mohammad Hosseinabady, José Luis Núñez-Yáñez, J. Núñez-Yáñez, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

بررسی تأثیر اولتراسوند بر نشانگرهای حاصل از کوفتگی عضلانی تأخیری (DOMS)

Mohammad Hosseinabady, Hamid Reza Taheri, Naghi Rahimi, 2011 .

Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips

Rafael Asenjo, Mohammad Hosseinabady, Angeles G. Navarro, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks

Mohammad Hosseinabady, Jose Nunez-Yanez, 2021, Array.

An Efficient Online BIST Architecture for NoCs

Zainalabedin Navabi, Mohammad Hosseinabady, Mahdi Nazm Bojnordi, 2006 .