Guerric de Streel

A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs

David Bol, François Botman, Denis Flandre, 2015, IEEE Journal of Solid-State Circuits.

A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range

David Bol, Numa Couniot, Guerric de Streel, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers

David Bol, Denis Flandre, François-Xavier Standaert, 2016, SPACE.

SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape

David Bol, Guerric de Streel, Charlotte Frenkel, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array

David Bol, Denis Flandre, Cecilia Gimeno, 2016, ICDSC.

Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools

David Bol, Guerric de Streel, François Stas, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level

David Bol, Guerric de Streel, 2014 .

Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology

David Bol, Guerric de Streel, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

An 802.15.4 IR-UWB Transmitter SoC with Adaptive-FBB-Based Channel Selection and Programmable Pulse Shape

David Bol, Guerric de Streel, 2020 .