Jun Hyun Chun

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces

Chulwoo Kim, Hoon Choi, Hyun-Woo Lee, 2012, IEEE J. Solid State Circuits.

A 10 Gb/s 4-PAM transceiver with adaptive pre-emphasis

Jun Hyun Chun, Jinwook Burm, Bongsub Song, 2011, 2011 International Symposium on Integrated Circuits.

An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM

Jaejin Lee, Jin-Hee Cho, Kyung Whan Kim, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications

Kyung-Tae Kim, Jun Hyun Chun, Jae-Beom Park, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface

Kyung Whan Kim, Jae-Hwan Kim, Jun Hyun Chun, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

High bandwidth memory(HBM) with TSV technique

Jaejin Lee, Kyung Whan Kim, Jun Hyun Chun, 2016, 2016 International SoC Design Conference (ISOCC).

A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits

Jaejin Lee, Jin-Hee Cho, Kyung Whan Kim, 2015, IEEE Journal of Solid-State Circuits.

Design considerations of HBM stacked DRAM and the memory architecture extension

Jaejin Lee, Kyung Whan Kim, Jun Hyun Chun, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology

Haris Pozidis, Evangelos Eleftheriou, Jun Hyun Chun, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

Chulwoo Kim, Hyun-Woo Lee, Yong-Hoon Kim, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.