Young-Jung Choi

发表

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces

Chulwoo Kim, Hoon Choi, Hyun-Woo Lee, 2012, IEEE J. Solid State Circuits.

A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology

Chulwoo Kim, Hyun-Woo Lee, Young-Jung Choi, 2011, IEEE Journal of Solid-State Circuits.

A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM

Young-Jung Choi, Kwan-Weon Kim, Joong-Sik Kih, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster

Young-Jung Choi, Byong-Tae Chung, Joo-Hwan Cho, 2010, 23rd IEEE International SOC Conference.

A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

Young-Jung Choi, Sang-Hoon Shin, Kwan-Weon Kim, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface

Chulwoo Kim, Hyun-Woo Lee, Yunsaing Kim, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A single-loop DLL using an OR-AND duty-cycle correction technique

Young-Jung Choi, Byong-Tae Chung, Kwan-Weon Kim, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

A One-Cycle Lock Time Slew-Rate-Controlled Output Driver

Chulwoo Kim, Young-Jung Choi, Hyung-Dong Lee, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface

Hyun-Woo Lee, Young-Jung Choi, Sang-Hoon Shin, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A fast-lock synchronous multi-phase clock generator based on a time-to-digital converter

Chulwoo Kim, Young-Jung Choi, Jabeom Koo, 2009, 2009 IEEE International Symposium on Circuits and Systems.

A 0.17–1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme

Chulwoo Kim, Suki Kim, Young-Jung Choi, 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application

Chulwoo Kim, Gil-Su Kim, Young-Jung Choi, 2009, 2009 IEEE Custom Integrated Circuits Conference.

A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface

Chulwoo Kim, Hyun-Woo Lee, Yunsaing Kim, 2012, 2012 IEEE International Solid-State Circuits Conference.

MOS varactor modeling for mm-Wave applications

In Man Kang, Hyungcheol Shin, Hakchul Jung, 2008, 2008 Asia-Pacific Microwave Conference.

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

Young-Jung Choi, Ki-Won Lee, Woo-Young Lee, 2007, IEEE Journal of Solid-State Circuits.

Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb/s GDDR5 DRAM interface

Young-Jung Choi, Woo-Young Lee, Jong-Ho Kang, 2009, 2009 Symposium on VLSI Circuits.

A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC

Chulwoo Kim, Young-Jung Choi, Kwan-Weon Kim, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

Chulwoo Kim, Hyun-Woo Lee, Young-Jung Choi, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

Hyun-Woo Lee, Young-Jung Choi, Byong-Tae Chung, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

SDTV Quality Assessment Using Energy Distribution of DCT Coefficients

Ho-Youl Jung, Ha-Joong Park, Young-Jung Choi, 2008, 2008 International Conference on Embedded Software and Systems.

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

Hyun-Woo Lee, Young-Jung Choi, Ji-Yeon Yang, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Coverage expandable current type code controlled DCC with TDC-based range selector

Suki Kim, Hyun-Woo Lee, Young-Jung Choi, 2009, IEICE Electron. Express.

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

Chulwoo Kim, Hyun-Woo Lee, Yong-Hoon Kim, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A low power and high performance robust digital delay locked loop against noisy environments

Young-Jung Choi, Byong-Tae Chung, Ki-Han Kim, 2008, 2008 IEEE Asian Solid-State Circuits Conference.