Matthias Braendli

发表

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

Thomas Toifl, Christian Menolfi, Hazar Yueksel, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design considerations for 50G+ backplane links

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os

Thomas Toifl, Christian Menolfi, Michael P. Beakes, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Yusuf Leblebici, Thomas Toifl, Martin L. Schmatz, 2013, IEEE Journal of Solid-State Circuits.

20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS

Johann W. Kolar, Thomas Toifl, Christian Menolfi, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

Volkan Cevher, Yusuf Leblebici, Thomas Toifl, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A DDR3/4 memory link TX supporting 24–40 Ω, 0.8–1.6 V, 0.8–5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI

Thomas Toifl, Christian Menolfi, Hazar Yueksel, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS

Yusuf Leblebici, Thomas Toifl, Martin L. Schmatz, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET

Thomas Toifl, Christian Menolfi, Yusuf Leblebici, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2013, 2013 Symposium on VLSI Circuits.

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS

Johann W. Kolar, Thomas Toifl, Christian Menolfi, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

An In-Comparator Aperture-Time Equalization in a 7-nm FinFET CMOS 40-Gb/s Receiver

Matthias Braendli, Pier Andrea Francese, Marcel Kossel, 2020, IEEE Solid-State Circuits Letters.

A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Energy-Efficient High-Speed SAR ADCs in CMOS

Thomas Toifl, Martin L. Schmatz, Christian Menolfi, 2015 .

A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2013, IEEE Journal of Solid-State Circuits.

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

Thomas Toifl, Christian Menolfi, Andrea Prati, 2012, IEEE Journal of Solid-State Circuits.

A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS

Yusuf Leblebici, Thomas Toifl, Martin L. Schmatz, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Yusuf Leblebici, Christian Menolfi, Alessandro Cevrero, 2020, IEEE Journal of Solid-State Circuits.

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

Yusuf Leblebici, Thomas Toifl, Martin L. Schmatz, 2016, IEEE Journal of Solid-State Circuits.

23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS

Thomas Toifl, Christian Menolfi, Andreas Peter Burg, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Multi-gigabit GCM-AES Architecture Optimized for FPGAs

Norbert Felber, Matthias Braendli, Johannes Wolkerstorfer, 2007, CHES.

A 28Gb/s source-series terminated TX in 32nm CMOS SOI

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS

Christian Menolfi, Andrea Prati, Matthias Braendli, 2012, IEEE Journal of Solid-State Circuits.

A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2014, IEEE Journal of Solid-State Circuits.

A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS

Thomas Toifl, Christian Menolfi, Andreas Peter Burg, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS

Thomas Toifl, Christian Menolfi, Hazar Yueksel, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Qiuting Huang, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Qiuting Huang, 2017, 2017 Symposium on VLSI Circuits.

CMOS ADCs Towards 100 GS/s and Beyond

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2016, 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Volkan Cevher, Yusuf Leblebici, Thomas Toifl, 2018, IEEE Journal of Solid-State Circuits.

A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

A 10-Bit 20–40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2018, 2018 IEEE Symposium on VLSI Circuits.

22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS

Matthias Braendli, Pier Andrea Francese, Thomas Morf, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Wide bandwidth room-temperature THz imaging array based on antenna-coupled MOSFET bolometer ☆

Thomas Toifl, Christian Menolfi, Ute Drechsler, 2014 .