Pier Andrea Francese

发表

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

Thomas Toifl, Christian Menolfi, Hazar Yueksel, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design considerations for 50G+ backplane links

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2018, IEEE Journal of Solid-State Circuits.

A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os

Thomas Toifl, Christian Menolfi, Michael P. Beakes, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

Mounir Meghelli, Andrea Prati, Pier Andrea Francese, 2013, IEEE Journal of Solid-State Circuits.

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Yusuf Leblebici, Thomas Toifl, Martin L. Schmatz, 2013, IEEE Journal of Solid-State Circuits.

20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS

Johann W. Kolar, Thomas Toifl, Christian Menolfi, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V

Thomas Toifl, Christian Menolfi, Georges Gielen, 2017, 2017 Symposium on VLSI Circuits.

A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

Volkan Cevher, Yusuf Leblebici, Thomas Toifl, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A DDR3/4 memory link TX supporting 24–40 Ω, 0.8–1.6 V, 0.8–5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI

Thomas Toifl, Christian Menolfi, Hazar Yueksel, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS

Yusuf Leblebici, Thomas Toifl, Martin L. Schmatz, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET

Thomas Toifl, Christian Menolfi, Yusuf Leblebici, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2013, 2013 Symposium on VLSI Circuits.

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS

Johann W. Kolar, Thomas Toifl, Christian Menolfi, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

An In-Comparator Aperture-Time Equalization in a 7-nm FinFET CMOS 40-Gb/s Receiver

Matthias Braendli, Pier Andrea Francese, Marcel Kossel, 2020, IEEE Solid-State Circuits Letters.

A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A deep trench capacitor based 2:1 and 3:2 reconfigurable on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS

Johann W. Kolar, Thomas Toifl, Christian Menolfi, 2014, 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014.

Energy-Efficient High-Speed SAR ADCs in CMOS

Thomas Toifl, Martin L. Schmatz, Christian Menolfi, 2015 .

A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2013, IEEE Journal of Solid-State Circuits.

A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS

Yusuf Leblebici, Thomas Toifl, Martin L. Schmatz, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

Yusuf Leblebici, Thomas Toifl, Martin L. Schmatz, 2016, IEEE Journal of Solid-State Circuits.

A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS

Yang You, Pier Andrea Francese, Marcel Kossel, 2020, 2020 IEEE Symposium on VLSI Circuits.

23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS

Thomas Toifl, Christian Menolfi, Andreas Peter Burg, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2018, IEEE Journal of Solid-State Circuits.

28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

ESSCIRC 2014 - 40th European Solid State Circuits Conference, Venice Lido, Italy, September 22-26, 2014

Christian Menolfi, Pier Andrea Francese, Marcel Kossel, 2014, ESSCIRC.

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS

Christian Menolfi, Andrea Prati, Matthias Braendli, 2012, IEEE Journal of Solid-State Circuits.

Deep learning acceleration based on in-memory computing

Nikolas Ioannou, Evangelos Eleftheriou, Pier Andrea Francese, 2019, IBM J. Res. Dev..

Encoder logic for reducing serial I/O power in sensors and sensor hubs

Martin C. Rinard, Phillip Stanley-Marbell, Pier Andrea Francese, 2016, 2016 IEEE Hot Chips 28 Symposium (HCS).

A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2014, IEEE Journal of Solid-State Circuits.

A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery

Johann W. Kolar, Thomas Toifl, Christian Menolfi, 2017, IEEE Transactions on Power Electronics.

A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS

Thomas Toifl, Christian Menolfi, Andreas Peter Burg, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS

Thomas Toifl, Christian Menolfi, Hazar Yueksel, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Qiuting Huang, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters

Johann W. Kolar, Thomas Toifl, Christian Menolfi, 2017, IEEE Transactions on Power Electronics.

A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency

Pier Andrea Francese, Maria Rosaria Tursi, Ols Hidri, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2017, IEEE Journal of Solid-State Circuits.

6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2018, IEEE Journal of Solid-State Circuits.

5 Parallel Prism: A topology for pipelined implementations of convolutional neural networks using computational memory pdf

Luca Benini, Thomas Parnell, Evangelos Eleftheriou, 2019, ArXiv.

A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency

Pier Andrea Francese, Maria Rosaria Tursi, Ols Hidri, 2009, IEEE Journal of Solid-State Circuits.

A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET

Thomas Toifl, Christian Menolfi, Qiuting Huang, 2017, 2017 Symposium on VLSI Circuits.

CMOS ADCs Towards 100 GS/s and Beyond

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2016, 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Volkan Cevher, Yusuf Leblebici, Thomas Toifl, 2018, IEEE Journal of Solid-State Circuits.

A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS

Thomas Toifl, Christian Menolfi, Andrea Prati, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

A 10-Bit 20–40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration

Thomas Toifl, Christian Menolfi, Alessandro Cevrero, 2018, 2018 IEEE Symposium on VLSI Circuits.

An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS

Christian Menolfi, Pier Andrea Francese, Marcel Kossel, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

D/A converters in CMOS technology

Pier Andrea Francese, 2005 .

22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS

Yusuf Leblebici, Thomas Toifl, Christian Menolfi, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS

Matthias Braendli, Pier Andrea Francese, Thomas Morf, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Efficient Pipelined Execution of CNNs Based on In-Memory Computing and Graph Homomorphism Verification

Luca Benini, Evangelos Eleftheriou, Pier Andrea Francese, 2021, IEEE Transactions on Computers.

Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

Peter Mueller, Pier Andrea Francese, Thomas Morf, 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, 2021, ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC).

Wide bandwidth room-temperature THz imaging array based on antenna-coupled MOSFET bolometer ☆

Thomas Toifl, Christian Menolfi, Ute Drechsler, 2014 .