Yvon Savaria

发表

SoC platform architecture for a network processor

Hany Ghattas, M. Mbaye, J. Pepga Bissou, 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

Very short locking time PLL based on controlled gain technique

Mohamad Sawan, Y. Fouzar, Yvon Savaria, 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

Fault tolerant smart transducer interfaces for safety-critical avionics applications

Yvon Savaria, Guchuan Zhu, Safwen Bouanen, 2013 .

System integration of high voltage electrostatic MEMS actuators

Mohamad Sawan, Yvon Savaria, Jean-François Saheb, 2005, The 3rd International IEEE-NEWCAS Conference, 2005..

A fast CMOS voltage-controlled ring oscillator

Yvon Savaria, D. Chtchvyrkov, J. F. Currie, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Zero skew differential clock distribution network

Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Are defected-tolerant circuits with redundancy really cost-effective?

Claude Thibeault, Yvon Savaria, Y. Gagnon, 1997 .

High Voltage Interfaces for CMOS/DMOS Technologies

Yvon Savaria, Jean-Francois Richard, Stéphane Martel, 2003 .

Probabilistic model checking of clock domain crossing interfaces

Otmane Aït Mohamed, Yvon Savaria, Mounir Boukadoum, 2012, 10th IEEE International NEWCAS Conference.

An ADPLL circuit using a DDPS for genlock applications

Nigel Seth-Smith, Yvon Savaria, Dorin Emil Calbaza, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

An Integrated Test Platform for Nanostructure Electrical Characterization

Yvon Savaria, O. Duval, L.-P. Lafrance, 2004 .

Direct digital frequency synthesis of low-jitter clocks

Yvon Savaria, D. E. Calbaza, 2001 .

Novel laser trimming technique for microelectronics

Michel Meunier, Yvon Savaria, Y. Gagnon, 2001, SPIE LASE.

Analysis of Resistive Open Defects in Drowsy SRAM Cells

Asim J. Al-Khalili, Yvon Savaria, Afshin Nourivand, 2011, J. Electron. Test..

10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 /spl mu/m CMOS

Yvon Savaria, Hung Tien Bui, 2004 .

An interconnection network for a novel reconfigurable circuit board

Olivier Valorge, Yvon Savaria, Nicolas Laflamme-Mayer, 2009 .

A Wafer-Scale Rapid Electronic Systems Prototyping Platform

Yvon Savaria, Yves Blaquiere, Walder Andre, 2011 .

Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL

Yves Blaquière, Yvon Savaria, Etienne Lepercq, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients

Otmane Aït Mohamed, Yvon Savaria, Ghaith Bany Hamad, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

Reliability Enhancement of Redundancy Management in AFDX Networks

Meng Li, Yvon Savaria, Michaël Lauer, 2017, IEEE Transactions on Industrial Informatics.

A direct digitally delay generator

Yvon Savaria, D. E. Calbaza, 2000, 2000 International Semiconductor Conference. 23rd Edition. CAS 2000 Proceedings (Cat. No.00TH8486).

A PowerPlanning ModelforImplantable Stimulators

Mohamad Sawan, Yvon Savaria, S. Hashemi, 2006 .

An interconnect-aware delay model for dynamic voltage scaling in NM technologies

Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria, 2009, GLSVLSI '09.

CMOS wide-swing differential VCO for fully integrated fast PLL

Mohamad Sawan, Yvon Savaria, Y. Fouzar, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

A tight end-to-end delay bound and scheduling optimization of an avionics AFDX network

Fei Hu, Jian Li, Xue Liu, 2011 .

A VLSI chip for 3-D camera calibration

Francois Blais, Yvon Savaria, J.-A. Beraldin, 1995, Proceedings 1995 Canadian Conference on Electrical and Computer Engineering.

Bit-Slicing FPGA Accelerator for Quantized Neural Networks

Yvon Savaria, Jean-Pierre David, Olexa Bilaniuk, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Bridging the Gap: FPGAs as Programmable Switches

Yvon Savaria, J. M. Pierre Langlois, Thibaut Stimpfling, 2020, 2020 IEEE 21st International Conference on High Performance Switching and Routing (HPSR).

Component-based methodology for hardware design of a dataflow processing network

Gabriela Nicolescu, Hany Ghattas, Yvon Savaria, 2005, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05).

Comparing results from defect-tolerant yield models

Claude Thibeault, Yvon Savaria, 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Neuromuscular Representation and Synthetic Generation of Handwritten Whiteboard Notes

Christian O'Reilly, Yvon Savaria, Andreas Fischer, 2014, 2014 14th International Conference on Frontiers in Handwriting Recognition.

Layerwise Noise Maximisation to Train Low-Energy Deep Neural Networks

Yvon Savaria, S'ebastien Henwood, Franccois Leduc-Primeau, 2019, 2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS).

An architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems

Yvon Savaria, Daniel Audet, N. Arel, 1994 .

Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures

Asim J. Al-Khalili, Yvon Savaria, Afshin Nourivand, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An interface for the I2C protocol in the WaferBoard™

Yvon Savaria, Wasim Hussain, Yves Blaquiere, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A study on split-output TSPC CMOS circuits

Yvon Savaria, S. Patenaude, B. Antaki, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Direct digital frequency synthesis of low-jitter clocks

Yvon Savaria, D. E. Calbaza, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

Design Intelligence for Interconnection Realization in Power-Managed SoCs

Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria, 2015, Computational Intelligence in Digital and Network Designs and Applications.

Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics

Yvon Savaria, Omar Al-Terkawi Hasib, Claude Thibeault, 2019, J. Electron. Test..

Estimation of energy performance in computing platforms

Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Repeater insertion in power-managed VLSI systems

Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria, 2011, GLSVLSI '11.

Activity management in battery-powered embedded systems: A case study of ZigBee® WSN

Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

A novel hybrid FIFO asynchronous clock domain crossing interfacing method

Otmane Aït Mohamed, Yvon Savaria, Syed Rafay Hasan, 2012, GLSVLSI '12.

Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA

Yvon Savaria, Yves Blaquiere, Safa Berrima, 2020, IET Circuits Devices Syst..

CNN2Gate: Toward Designing a General Framework for Implementation of Convolutional Neural Networks on FPGA pdf

Yvon Savaria, Alireza Ghaffari, Y. Savaria, 2020, ArXiv.

Multiple targets direction-of-arrival estimation in frequency scanning array antennas

Yvon Savaria, Jean-Jacques Laurin, Mona Akbarniai Tehrani, 2016 .

A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits

Yvon Savaria, Claude Thibeault, Maryem Benyoussef, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

A BiCMOS wide-lock range fully integrated PLL

Mohamad Sawan, Y. Fouzar, Yvon Savaria, 1998, Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186).

A direct digital period synthesis circuit

Yvon Savaria, D. E. Calbaza, 2002 .

Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain

Yves Blaquière, Yvon Savaria, Safa Berrima, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI

Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.