Jen-Chieh Liu

发表

A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection

Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit

Jen-Chieh Liu, Kuo-Hsing Cheng, Kai-Wei Hong, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A wide supply voltage range and low-power all-digital clock generator

Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, 2013 .

A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator

Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

All digital phase-locked loop using active inductor oscillator and novel locking algorithm

Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

A radio-controlled receiver for clocks/watches and alarm applications

Jia-Hung Peng, Jen-Chieh Liu, Hong-Yi Huang, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs

Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, 2017 .

A 64-MHz∼640-MHz 64-phase clock generator

Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler

Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture

Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, 2016, IEICE Trans. Electron..

All-Digital PLL Using Pulse-Based DCO

Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

A loading effect insensitive and high precision clock synchronization circuit

Kuo-Hsing Cheng, Jen-Chieh Liu, Kai-Wei Hong, 2010, 2010 Proceedings of ESSCIRC.

A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution

Jen-Chieh Liu, Chao-Jen Huang, Pei-Ying Lee, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, 2016, IEICE Electron. Express.

A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration

Ming-Dou Ker, Jen-Chieh Liu, Yu Lee, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Measurement error analysis and calibration techniques for built-in jitter measurement circuit

Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

A Low Power Pulse Generator for Test Platform Applications

Jen-Chieh Liu, Pei-Ying Lee, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique

Jen-Chieh Liu, Yu-Lung Lo, Hsi-Hua Wang, 2018 .

Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator

Jen-Chieh Liu, Kuo-Hsing Cheng, Shu-Yu Jiang, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A low-jitter all-digital PLL with high-linearity DCO

Yu-Lung Lo, Jen-Chieh Liu, Chun-Yen Yu, 2018 .

Low supply voltage and multiphase all-digital crystal-less clock generator

Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, 2018, IET Circuits Devices Syst..

0.5V 160-MHz 260uW all digital phase-locked loop

Wei-Bin Yang, Jen-Chieh Liu, Kuo-Hsing Cheng, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit

Jen-Chieh Liu, Hong-Yi Huang, Bo-Ruei Wang, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A chaotically injected timing technique for ring-based oscillators

Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Auto-calibration techniques in built-in jitter measurement circuit

Jen-Chieh Liu, Kuo-Hsing Cheng, Chih-Ping Cheng, 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).