Konstantinos Tatas

发表

Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms

Antonios Argyriou, Dimitrios Soudris, Minas Dasygenis, 2003, Real Time Imaging.

Fine-Grain reconfigurable platform: FPGA hardware design and software toolset development

Spiridon Nikolaidis, Konstantinos Tatas, Kostas Siozios, 2005 .

Power, performance and area exploration of block matching algorithms mapped on programmable processors

Antonios Argyriou, Dimitrios Soudris, Minas Dasygenis, 2001, Proceedings 2001 International Conference on Image Processing (Cat. No.01CH37205).

FPGA Architecture Design and Toolset for Logic Implementation

Dimitrios Soudris, Stilianos Siskos, Spiridon Nikolaidis, 2003, PATMOS.

Power and performance exploration of embedded systems executing multimedia kernels

Antonios Argyriou, Dimitrios Soudris, Minas Dasygenis, 2002 .

A complete platform and toolset for system implementation on fine-grain reconfigurable hardware

Dimitrios Soudris, Stilianos Siskos, Spiridon Nikolaidis, 2005, Microprocess. Microsystems.

Fuzzy classification of OpenCL programs targeting heterogeneous systems

Konstantinos Tatas, Costas Kyriacou, Ahmad Al-Zoubi, 2020, J. Intell. Fuzzy Syst..

Cache-aware network-on-chip for chip multiprocessors

Konstantinos Tatas, Demetris Demetriou, Anastasia Christou, 2009, Microtechnologies.

An integrated FPGA design framework: custom designed FPGA platform and application mapping toolset development

Dimitrios Soudris, Stilianos Siskos, Spiridon Nikolaidis, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

Projects on Network-on-Chip

Axel Jantsch, Konstantinos Tatas, Kostas Siozios, 2014 .

Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms

Dimitrios Soudris, Kostas Masselos, Adonios Thanailakis, 2003, PATMOS.

Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms

Dimitrios Soudris, Adonios Thanailakis, Konstantinos Tatas, 2005, J. Embed. Comput..

NoC Verification and Testing

Axel Jantsch, Konstantinos Tatas, Dimitrios Soudris, 2014 .

Hardware implementation of dynamic fuzzy logic based routing in Network-on-Chip

Konstantinos Tatas, Chrysostomos Chrysostomou, K. Tatas, 2017, Microprocess. Microsystems.

A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC

Dimitrios Soudris, Alexandros Bartzas, Konstantinos Tatas, 2013, Int. J. Adapt. Resilient Auton. Syst..

A memory management approach for efficient implementation of multimedia kernels on programmable architectures

Antonios Argyriou, Dimitrios Soudris, N. Kroupis, 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

Low-cost fault-tolerant routing for regular topology NoCs

Konstantinos Tatas, Costas Kyriacou, S. Sawa, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications

Dimitrios Soudris, Adonios Thanailakis, Konstantinos Tatas, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

High-performance 3D NoC bufferless router with approximate priority comparison

Konstantinos Tatas, 2018, 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST).

NoC-Based System Integration

Axel Jantsch, Konstantinos Tatas, Dimitrios Soudris, 2014 .

Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs

Paraskevas Evripidou, Stephan Wong, Pedro Trancoso, 2008, Parallel Process. Lett..

A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems

Dimitrios Soudris, Adonios Thanailakis, Konstantinos Tatas, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Power and performance exploration of embedded systems executing multimedia kernels : Low-power systems-on-chip

Dimitrios Soudris, Minas Dasygenis, N. Kroupis, 2002 .

Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms

Dimitrios Soudris, Adonios Thanailakis, Konstantinos Tatas, 2003, FPL.

Designing 2D and 3D Network-on-Chip Architectures

Axel Jantsch, Konstantinos Tatas, Dimitrios Soudris, 2013 .

Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications

Dimitrios Soudris, Adonios Thanailakis, Konstantinos Tatas, 2007, Integr..

Implementation of a threaded dataflow multiprocessor using FPGAs

Konstantinos Tatas, Costas Kyriacou, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

Antonios Argyriou, Dimitrios Soudris, Minas Dasygenis, 2006, J. VLSI Signal Process..

Towards Dynamic Multi-task Schedulling of OpenCL Programs on Emerging CPU-GPU-FPGA Heterogeneous Platforms: A Fuzzy Logic Approach

Konstantinos Tatas, Costas Kyriacou, Ahmad Al-Zoubi, 2018, 2018 IEEE International Conference on Cloud Computing Technology and Science (CloudCom).

Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications

Antonios Argyriou, Dimitrios Soudris, Minas Dasygenis, 2000, PATMOS.

A novel fuzzy logic based bufferless routing algorithm for low-power NoCs

Konstantinos Tatas, Chrysostomos Chrysostomou, 2012, 2012 2nd Baltic Congress on Future Internet Communications.

Power and Thermal Effects and Management

Axel Jantsch, Konstantinos Tatas, Dimitrios Soudris, 2014 .

DAGGER: a novel generic methodology for FPGA bitstream generation and its software tool implementation

Dimitrios Soudris, Adonios Thanailakis, Konstantinos Tatas, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

A reusable IP FFT core for DSP applications

Dimitrios Soudris, Kostas Masselos, Adonios Thanailakis, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Network-on-Chip Technology: A Paradigm Shift

Axel Jantsch, Konstantinos Tatas, Kostas Siozios, 2014 .

A novel methodology for designing high-performance and low-energy FPGA routing architecture

Dimitrios Soudris, Adonios Thanailakis, Konstantinos Tatas, 2006, FPGA '06.

NoC Modeling and Topology Exploration

Axel Jantsch, Konstantinos Tatas, Kostas Siozios, 2014 .

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications

Dimitrios Soudris, Stilianos Siskos, Spiridon Nikolaidis, 2005, IEICE Trans. Inf. Syst..

A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development

Dimitrios Soudris, Adonios Thanailakis, Konstantinos Tatas, 2004, FPL.

The Spidergon STNoC

Axel Jantsch, Konstantinos Tatas, Dimitrios Soudris, 2014 .

A Survey of Existing Fine-Grain Reconfigurable Architectures and CAD tools

Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, 2007 .

3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D Networks-on-Chip

Konstantinos Tatas, Costas Kyriacou, Savvas Sava, 2017, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

A novel division algorithm for parallel and sequential processing

Dimitrios Soudris, Minas Dasygenis, Konstantinos Tatas, 2002, 9th International Conference on Electronics, Circuits and Systems.

Data and instruction memory exploration of embedded systems for multimedia applications

Antonios Argyriou, Dimitrios Soudris, Minas Dasygenis, 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

A full adder based methodology for scaling operation in residue number system

Dimitrios Soudris, Minas Dasygenis, Adonios Thanailakis, 2002, 9th International Conference on Electronics, Circuits and Systems.

A Novel Division Algorithm and Architectures for Parallel and Sequential Processing

Dimitrios Soudris, Adonios Thanailakis, Konstantinos Tatas, 2005, J. Circuits Syst. Comput..

A Dynamic Fuzzy Logic Based Routing Scheme for Bufferless NoCs

Konstantinos Tatas, Chrysostomos Chrysostomou, A. R. Runcan, 2012, 2012 IEEE 15th International Conference on Computational Science and Engineering.

Middleware Memory Management in NoC

Axel Jantsch, Konstantinos Tatas, Dimitrios Soudris, 2014 .

An integrated framework for architecture level exploration of reconfigurable platform

Dimitrios Soudris, Adonios Thanailakis, Konstantinos Tatas, 2005, International Conference on Field Programmable Logic and Applications, 2005..

On Designing 3-D Platforms

Axel Jantsch, Konstantinos Tatas, Dimitrios Soudris, 2014 .

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow

Dimitrios Soudris, Stilianos Siskos, Spiridon Nikolaidis, 2005, ASP-DAC.

The SYSMANTIC NoC Design and Prototyping Framework

Axel Jantsch, Konstantinos Tatas, Dimitrios Soudris, 2014 .

Rapid High-Level FPGA Resource Estimation for a Novel Heterogeneous Platform Scheduling Scheme

Konstantinos Tatas, Ahmad Al-Zoubi, 2020, 2020 11th International Conference on Information and Communication Systems (ICICS).

Design space exploration of the KNN imputation on FPGA

Konstantinos Tatas, Costas Kyriacou, Ahmad Al-Zoubi, 2018, 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Adaptive Networks-on-Chip Routing with Fuzzy Logic Control

Konstantinos Tatas, Chrysostomos Chrysostomou, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

Memory hierarchy optimization of multimedia applications on programmable embedded cores

Antonios Argyriou, Dimitrios Soudris, Minas Dasygenis, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations

Dimitrios Soudris, Kostas Masselos, Adonios Thanailakis, 2002, FPL.

iPONICS: IoT Monitoring and Control for Hydroponics

Konstantinos Tatas, Ahmad Al-Zoubi, Andreas Antoniou, 2021, 2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Towards an Analytical Model of Latency in Deflection Routing: A Stochastic Process Approach for Bufferless NoCs

Konstantinos Tatas, K. Tatas, 2021, 2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST).