Yves Morand

发表

A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

Pierre Morin, Sylvain Maitrejean, Frederic Allibert, 2016 .

Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes

O. Rozeau, Yves Morand, Emmanuel Dubois, 2014 .

Source and Drain Contact Module for FDSOI MOSFETs : Silicidation and Strain Engineering

David Cooper, Yves Morand, Jean-Michel Hartmann, 2013 .

Process for manufacturing a capacitor in an integrated circuit, and integrated circuit corresponding

Yves Morand, Jean Luc Pelloie, 2000 .

Influence of Annealing Treatments on the Morphology and Electrical Properties of GeOI Substrates Obtained by Ge Condensation

Yves Morand, Yves Campidelli, S. Cristoloveanu, 2007 .

Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect

Yves Morand, Christian Arvet, T. Mourier, 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

Planar Double Gate CMOS transistors with 40nm metal gate for multipurpose applications

Sylvain Maitrejean, Yves Morand, Maud Vinet, 2004 .

Review of Some Critical Aspects of Ge and GeOI Substrates

Yves Morand, Simon Deleonibus, Laurent Clavelier, 2006 .

Multilevel test structures for metal CMP integration application to Cu/SiO/sub 2/ damascene interconnect

Yves Morand, M. Fayolle, P. Gayet, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

Junction technology outlook for sub-28nm FDSOI CMOS

Laurent Grenouillet, Yves Morand, Maud Vinet, 2014, 2014 International Workshop on Junction Technology (IWJT).

Ω-Gate Nanowire Transistors Realized by Sidewall Image Transfer Patterning: 35nm Channel Pitch and Opportunities for Stacked-Nanowires Architectures

Yves Morand, Stephane Monfray, Frederic Boeuf, 2015 .

Copper metallization for advanced IC: requirements and technological solutions

Yves Morand, Y. Morand, 1999 .

The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?

Yves Morand, Yves Campidelli, Sorin Cristoloveanu, 2008 .

A New Method to Induce Tensile Stress in Silicon on Insulator Substrate: From Material Analysis to Device Demonstration

Pierre Morin, Sylvain Maitrejean, Nicolas Loubet, 2015 .

Fabrication of SiGe-on-insulator substrates by a condensation technique: an experimental and modelling study

Yves Morand, Laurent Clavelier, C. Licitra, 2007 .

MIM HfO/sub 2/ low leakage capacitors for eDRAM integration at interconnect levels

Yves Morand, Gilles Reimbold, Serge Blonkowski, 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

Thermal stability enhancement of Ni-based silicides, germano-silicides and germanides using W and F implantation for 3D CMOS sequential integration

Yves Morand, Perrine Batude, Louis Hutin, 2014, 2014 International Workshop on Junction Technology (IWJT).

High quality Germanium On Insulator wafers with excellent hole mobility

Yves Morand, Sorin Cristoloveanu, Laurent Clavelier, 2007 .