Maud Vinet

发表

A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

Pierre Morin, Sylvain Maitrejean, Frederic Allibert, 2016 .

Design considerations for optimization of pull-in stability margin in electrostatic N/MEM relays

Maud Vinet, Giulia Usai, Louis Hutin, 2017, 2017 IEEE International Conference on IC Design and Technology (ICICDT).

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K

Maud Vinet, Bruna Cardoso Paz, Renan Trevisoli Doria, 2017, Microelectron. Reliab..

19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot

Maud Vinet, Marc Sanquer, Gaël Pillonnet, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs

A. Pofelski, Maud Vinet, R. Ranica, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

Towards high density 3D interconnections

Maud Vinet, Perrine Batude, Séverine Cheramy, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Thin-Film FD-SOI BIMOS Topologies for ESD Protection

Maud Vinet, Sorin Cristoloveanu, Philippe Galy, 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

Cost model for monolithic 3D integrated circuits

Fabien Clermidy, Maud Vinet, Daniel Gitlin, 2016, 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration

Maud Vinet, Mikaël Casse, Laurent Brunet, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

SOI CMOS technology for quantum information processing

Maud Vinet, Marc Sanquer, Sylvain Barraud, 2017, 2017 IEEE International Conference on IC Design and Technology (ICICDT).

Guidelines for intermediate back end of line (BEOL) for 3D sequential integration

Maud Vinet, M.-P. Samson, Charles-Antoine Guérin, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

3D High Density: technology, roadmap and applications

Maud Vinet, Perrine Batude, Lucile Arnaud, 2017 .

Variance Analysis in 3-D Integration: A Statistically Unified Model With Distance Correlations

Maud Vinet, Laurent Fesquet, Laurent Brunet, 2019, IEEE Transactions on Electron Devices.

Delay partitioning helps reducing variability in 3DVLSI

Maud Vinet, Laurent Fesquet, Olivier Rozeau, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Invited) 3D Monolithic Integration

Maud Vinet, Laurent Brunet, Perrine Batude, 2018 .

3D monolithic integration

Cyrille Le Royer, Maud Vinet, Simon Deleonibus, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices

Maud Vinet, Mikaël Casse, Laurent Brunet, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

The Coupled Atom Transistor: A first realization with shallow donors implanted in a FDSOI silicon nanowire

Romain Wacquez, Maud Vinet, Marc Sanquer, 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Piezoresistive transduction optimization of p-doped poly-Silicon NEMS

Maud Vinet, Thomas Ernst, Laurent Duraffourg, 2015, 2015 45th European Solid State Device Research Conference (ESSDERC).

Multigate silicon MOSFETs for 45 nm node and beyond

O. Faynot, Maud Vinet, S. Deleonibus, 2006 .

Towards high density 3D interconnections

Maud Vinet, Perrine Batude, Séverine Cheramy, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies

Maud Vinet, Sorin Cristoloveanu, Philippe Galy, 2017, 2017 IEEE International Conference on IC Design and Technology (ICICDT).

Variability in Fully Depleted MOSFETs

Laurent Grenouillet, Romain Wacquez, Maud Vinet, 2012, 2012 IEEE International Conference on IC Design & Technology.

(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities

Maud Vinet, Stephane Monfray, Frederic Boeuf, 2016 .

Ultra-Thin Body and BOX (UTBB) Device for Aggressive Scaling of CMOS Technology

Nicolas Loubet, Ali Khakifirooz, Maud Vinet, 2011 .

Plenary) The Future of Heterogeneous and Diversified ULSI Nanoelectronics

Maud Vinet, F. Andrieu, Simon Deleonibus, 2013 .

Planar bonded double gate mos transistors down to LG = 10nm

Maud Vinet, S. Deleonibus, J. Widiez, 2005 .

Analog performance of strained SOI nanowires down to 10K

Maud Vinet, Bruna Cardoso Paz, Mikaël Casse, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit

Olivier Billoint, Maud Vinet, Sebastien Thuries, 2018, 2018 International Conference on IC Design & Technology (ICICDT).

A method of making an electronic circuit integrated three-dimensional

Maud Vinet, Bernard Previtali, 2015 .

Generalized cost model for 3D systems

Maud Vinet, Olivier Faynot, Jean-Rene Lequepeys, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Opportunities brought by sequential 3D CoolCube™ integration

Gerald Cibrario, Olivier Billoint, Fabien Clermidy, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Revisited approach for the characterization of Gate Induced Drain Leakage

Maud Vinet, Gerard Ghibaudo, Perrine Batude, 2011 .

Variability of planar Ultra-Thin Body and Buried oxide (UTBB) FDSOI MOSFETs

J. Mazurier, Cyrille Le Royer, Maud Vinet, 2014, 2014 IEEE International Conference on IC Design & Technology.

Si MOS technology for spin-based quantum computing

Maud Vinet, Marc Sanquer, Sylvain Barraud, 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

Fine charge sensing using a silicon nanowire for biodetection

Maud Vinet, Sylvain Barraud, Thomas Ernst, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

System on Wafer: A New Silicon Concept in SiP

Maud Vinet, Alan Mathewson, Léa Di Cioccio, 2009, Proceedings of the IEEE.

Delay partitioning helps reducing variability in 3DVLSI

Maud Vinet, Laurent Fesquet, Olivier Rozeau, 2016 .

Towards a scalable quantum computer

Maud Vinet, Louis Hutin, Edoardo Charbon, 2018, 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part II: DC and AC Model Description

O. Rozeau, Maud Vinet, Thierry Poiroux, 2015, IEEE Transactions on Electron Devices.

Development of KrF hybrid resist for a dual-isolation application

Laurent Grenouillet, Maud Vinet, Bruce B. Doris, 2013, Advanced Lithography.

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

Romain Wacquez, Maud Vinet, Marc Sanquer, 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Emerging nano-devices for IOT applications

Fabien Clermidy, Maud Vinet, Louis Hutin, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

An analysis of stress evolution in stacked GAA transistors

Sylvain Maitrejean, Emmanuel Augendre, Nicolas Loubet, 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).

Session #8 SOI radiation effects and RF applications

Maud Vinet, Subu Iyer, 2008, 2008 IEEE International SOI Conference.

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Maud Vinet, Sylvain Barraud, Olivier Faynot, 2021, ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC).

MOS technology for quantum computing: recent progress and perspectives for scaling up

Maud Vinet, Mikaël Casse, Gérard Billiot, 2021, 2021 Device Research Conference (DRC).

A New Method for Series Resistance Extraction of Nanometer MOSFETs

Maud Vinet, Sylvain Barraud, Gilles Reimbold, 2017, IEEE Transactions on Electron Devices.

Analog performance of n- and p-FET SOI nanowires including channel length and temperature influence

Maud Vinet, Sylvain Barraud, Gilles Reimbold, 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Direct detection of a transport-blocking trap in a nanoscaled silicon single-electron transistor by radio-frequency reflectometry

Maud Vinet, Sylvain Barraud, Patrick Fay, 2014 .

Planar Double Gate CMOS transistors with 40nm metal gate for multipurpose applications

Sylvain Maitrejean, Yves Morand, Maud Vinet, 2004 .

Modeling of Fermi-Level Pinning Alleviation With MIS Contacts: n and pMOSFETs Cointegration Considerations—Part II

Maud Vinet, Emmanuel Dubois, Sebastien Martinie, 2016, IEEE Transactions on Electron Devices.

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration

Maud Vinet, Claire Fenouillet-Beranger, D. Lafond, 2015 .

Towards a Three-Dimensional Back-Illuminated Miniaturized CMOS Pixel Technology using 100nm Inter-Layer Contacts

Maud Vinet, Pierre Magnan, Perrine Batude, 2009 .

Junction technology outlook for sub-28nm FDSOI CMOS

Laurent Grenouillet, Yves Morand, Maud Vinet, 2014, 2014 International Workshop on Junction Technology (IWJT).