Rishita Saini

SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

Bishwajeet Pandey, D. M. Akbar Hussain, Meenakshi Bansal, 2014, 3rd International Symposium on Environmental Friendly Energies and Applications (EFEA).

FPGA Based Low Power ROM Design Using Capacitance Scaling

Bishwajeet Pandey, D. M. Akbar Hussain, Meenakshi Bansal, 2014 .

Low Power High Performance ROM Design on FPGA Using LVDCI I/O Standard

Bishwajeet Pandey, Meenakshi Bansal, Neha Bansal, 2014, 2014 International Conference on Computational Intelligence and Communication Networks.

LVCMOS I/O standard based environment friendly low power ROM design on FPGA

Bishwajeet Pandey, Meenakshi Bansal, Neha Bansal, 2015, 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom).

Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA

Bishwajeet Pandey, Meenakshi Bansal, Neha Bansal, 2014 .