Youngtag Woo

Quantitative Projections of the Cost Benefits of 3D Integration

Shan Gao, Irene Lin, Geert Van der Plas, 2015 .

SRAM cell performance analysis beyond 10-nm FinFET technology

Youngtag Woo, Sanjay Parihar, Motoi Ichihashi, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Design and process technology co-optimization with SADP BEOL in sub-10nm SRAM bitcell

Lei Yuan, Jongwook Kye, Youngtag Woo, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Study of cut mask lithography options for sub-20nm metal routing

Chenchen Wang, Yan Wang, Jongwook Kye, 2015, Advanced Lithography.

10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed Application

Vivek Joshi, Youngtag Woo, Motoi Ichihashi, 2018, 2018 31st IEEE International System-on-Chip Conference (SOCC).

Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for 10nm technology nodes and beyond

Jia Zeng, Youngtag Woo, Sriram Madhavan, 2016, SPIE Advanced Lithography.

Performance Boost Scheme with Activated Dummy Fin in 12-nm FinFET Technology for High-Performance Logic Application

Youngtag Woo, Chenchen Wang, Motoi Ichihashi, 2020, 2020 21st International Symposium on Quality Electronic Design (ISQED).