Ryosuke Noguchi

A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS

Hideyuki Nosaka, Akira Tsuchiya, Shinsuke Nakano, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS

Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, 2019, 2019 International SoC Design Conference (ISOCC).

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS

Hideyuki Nosaka, Shinsuke Nakano, Masafumi Nogawa, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

FPGA-Based Binary Labeling Signal Transmission System

Akira Tsuchiya, Ryosuke Noguchi, Keiji Kishine, 2019 .

Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier

Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, 2019, 2019 32nd IEEE International System-on-Chip Conference (SOCC).

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology

Hidetoshi Onodera, Akira Tsuchiya, Ryosuke Noguchi, 2018, 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS).

A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion

Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).