Keiji Kishine

发表

A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS

Hideyuki Nosaka, Akira Tsuchiya, Shinsuke Nakano, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS

Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, 2019, 2019 International SoC Design Conference (ISOCC).

Parallel multiple electric power conversion system constructed by connecting three power converters

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2013, 2013 International Conference on Electrical Machines and Systems (ICEMS).

Optimization Technique of Memory Traffic for FPGA-Based Image Processing System

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2019, 2019 International SoC Design Conference (ISOCC).

Low-jitter, low-power 2.5-Gb/s one-chip optical receiver IC with 1:8 DEMUX

Keiji Kishine, Haruhiko Ichino, Masaki Hirose, 1999, Proceedings of the 1999 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.99CH37024).

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity

Hidetoshi Onodera, Akira Tsuchiya, Toshiyuki Inoue, 2019, IEICE Trans. Electron..

FPGA-based transceiver circuit for labeling signal transmission system

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2017, 2017 International SoC Design Conference (ISOCC).

Design of On-Chip Multi-layered Inductor for Area-Efficient Inductive Peaking

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2020, 2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

Burst-Mode CMOS Transimpedance Amplifier Based on a Regulated-Cascode Circuit with Gain-Mode Switching

Keiji Kishine, Makoto Nakamura, Takuya Kojima, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Jitter-suppressed low-power 2.5 Gbit/s clock and data recovery IC without high-Q components

Noboru Ishihara, Keiji Kishine, Haruhiko Ichino, 1997 .

Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System

Hidetoshi Onodera, Akira Tsuchiya, Keiji Kishine, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS

Hidetoshi Onodera, Hiroshi Inoue, Akira Tsuchiya, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[REGULAR PAPER] Design Method for Active-shunt-feedback Type Inductorless Low-noise Amplifiers in 65-nm CMOS

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2020 .

2.5 Gbit/s clock and data recovery circuit IC using novel duplicated PLL technique

Keiji Kishine, Haruhiko Ichino, K. Takiguchi, 1999 .

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector

Hiroshi Inoue, Akira Tsuchiya, Kosuke Furuichi, 2016, 2016 International SoC Design Conference (ISOCC).

A wideband differential VCO based on double-short-path loop architecture

Keiji Kishine, Daisuke Ito, Makoto Nakamura, 2019, 2019 International SoC Design Conference (ISOCC).

25-Gb/s inductorless output buffer circuit with a pre-emphasis in 65-nm CMOS

Akira Tsuchiya, Keiji Kishine, Hiromi Inaba, 2014, 2014 International SoC Design Conference (ISOCC).

A Jitter Suppression Technique for a Clock Multiplier

Keiji Kishine, Haruhiko Ichino, K. Ishii, 2000 .

Low-Power 2.5-Gb/s Si-Bipolar IC Chipset for Optical Receivers and Transmitters Using Low-Voltage and Adjustment-Free Circuit Techniques

Noboru Ishihara, Keiji Kishine, Haruhiko Ichino, 1999 .

Low-jitter design method based on Wn-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

Hidetoshi Onodera, Keiji Kishine, Hiromi Inaba, 2009 .

Acquisition-time estimation for over 10 Gbit/s clock and data recovery ICs

Hidetoshi Onodera, Keiji Kishine, 2005 .

MAC protocol based on cross-layer design methodology for fast link in wireless communication systems

Keiji Kishine, Haruhiko Ichino, Shoko Ohteru, 2007, IEICE Electron. Express.

Frequency Discriminator Using a Simple AD Converter for Interface Systems

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2019, 2019 International SoC Design Conference (ISOCC).

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS

Hiroshi Koizumi, Keiji Kishine, Makoto Nakamura, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops

Hidetoshi Onodera, Hiroshi Inoue, Akira Tsuchiya, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

System construction method of parallel operation system constructed with three electric power converters

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2014, 2014 17th International Conference on Electrical Machines and Systems (ICEMS).

Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs-Duplicated Loop Control CDR-

Noboru Ishihara, Keiji Kishine, Haruhiko Ichino, 2001 .

Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors

Hidetoshi Onodera, Akira Tsuchiya, Keiji Kishine, 2011, 2011 International SoC Design Conference.

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS

Hideyuki Nosaka, Shinsuke Nakano, Masafumi Nogawa, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A-1-19 Simplification of Labeling Signal Detecting Circuit Using a Delay Detection Circuit

Keiji Kishine, Hiromi Inaba, Tomoki Tanaka, 2016 .

A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit

Keiji Kishine, Haruhiko Ichino, Kiyoshi Ishii, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Examination of cross current suppression method using control of parallel operation system constructed by two electric power converters

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2014, 2014 17th International Conference on Electrical Machines and Systems (ICEMS).

A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS

Hidetoshi Onodera, Akira Tsuchiya, Keiji Kishine, 2012, 17th Asia and South Pacific Design Automation Conference.

FPGA-Based Binary Labeling Signal Transmission System

Akira Tsuchiya, Ryosuke Noguchi, Keiji Kishine, 2019 .

A Wideband Differential VCO Based on Multiple-path Loop Architecture

Keiji Kishine, Makoto Nakamura, Daisuke Ito, 2018, 2018 International SoC Design Conference (ISOCC).

Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier

Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, 2019, 2019 32nd IEEE International System-on-Chip Conference (SOCC).

Throughput Estimation Method in Burst ACK Scheme for Optimizing Frame Size and Burst Frame Number Appropriate to SNR-Related Error Rate

Keiji Kishine, Shoko Ohteru, K. Kishine, 2010, IEICE Trans. Commun..

10-Gb/s Data Frame Generation Circuit with Frequency Modulation in 65-nm CMOS

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2018 .

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS

Hidetoshi Onodera, Akira Tsuchiya, Keiji Kishine, 2010, IEEE Custom Integrated Circuits Conference 2010.

Design of High-linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2017 .

Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control

Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

Simple Routing Control System for 10 Gb/s Data Transmission Using a Frequency Modulation Technique

Keiji Kishine, Hiromi Inaba, Tomoki Tanaka, 2016 .

Cross current suppression control for parallel operation system constructed with two electric power converters under different output

Keiji Kishine, Hiromi Inaba, Keisuke Ishikura, 2016, 2016 19th International Conference on Electrical Machines and Systems (ICEMS).

Simulation analysis of control methods for parallel multi-operating system constructed by the same output power converters

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2013, 2013 International Conference on Electrical Machines and Systems (ICEMS).

Study of three inputs combination reactor of parallel operation systems constructed with multiple electric power converters

Keiji Kishine, Hiromi Inaba, Keisuke Ishikura, 2015, 2015 18th International Conference on Electrical Machines and Systems (ICEMS).

Compact implementation IIR filter in FPGA for noise reduction of sensor signal

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2017, 2017 International SoC Design Conference (ISOCC).

Method controlling two or more sets of PMSM by one inverter on a railway vehicle

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2013, 2013 International Conference on Electrical Machines and Systems (ICEMS).

Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2016, 2016 International SoC Design Conference (ISOCC).

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology

Hidetoshi Onodera, Akira Tsuchiya, Ryosuke Noguchi, 2018, 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS).

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

Akira Tsuchiya, Keiji Kishine, Hiromi Inaba, 2016 .

Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks

Osamu Ishida, Keiji Kishine, Haruhiko Ichino, 2005, IEICE Trans. Commun..

A fast-response and high-sensitivity PIN-TIA module with wide dynamic range for 10 G burst-mode transmissions

Keiji Kishine, Kazuyoshi Nishimura, Makoto Nakamura, 2007 .

Design method of cross current suppression control for parallel operation system constructed with two electric power converters

Keiji Kishine, Hiromi Inaba, Keisuke Ishikura, 2015, 2015 18th International Conference on Electrical Machines and Systems (ICEMS).

Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2016, 2016 International SoC Design Conference (ISOCC).

A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion

Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS

Hidetoshi Onodera, Akira Tsuchiya, Keiji Kishine, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Driving parameter survey and experiment on railway drive system by using two or more permanent magnet synchronous motors controlled using one inverter

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2015, 2015 18th International Conference on Electrical Machines and Systems (ICEMS).

Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2017, 2017 International SoC Design Conference (ISOCC).

A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS

Hidetoshi Onodera, Akira Tsuchiya, Keiji Kishine, 2011, 2011 International SoC Design Conference.

Method controlling four sets of permanent magnet synchronous motor by one inverter on a railway vehicle

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2014, 2014 17th International Conference on Electrical Machines and Systems (ICEMS).

Simple and Low Power Highly Sensitive Frequency Demodulator Circuit for 10-Gb/s Transmission System for Labeling Signal

Hiromu Uemura, Keiji Kishine, Hiromi Inaba, 2017 .

Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2021, 2021 International Conference on Electronics, Information, and Communication (ICEIC).

Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Dynamic Memory Access Control for Accelerating FPGA-based Image Processing

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2021 .

5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2021, 2021 International Conference on Electronics, Information, and Communication (ICEIC).

A 10.3125-Gbit/s SiGe BiCMOS Burst-Mode 3R Receiver for 10G-EPON Systems

Jun Terada, Keiji Kishine, Takamasa Imai, 2007, OFC 2007.

10.3 Gbit/s burst-mode PIN-TIA module with high sensitivity, wide dynamic range and quick response

Keiji Kishine, Kazuyoshi Nishimura, Shunji Kimura, 2008 .

A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

Keiji Kishine, Haruhiko Ichino, H. Ichino, 2002 .